Semiconductor diodes employing back-side semiconductor or metal
Integrated circuit (IC) strata including one or more transistor and one or more semiconductor diode. A transistor may include one or more non-planar semiconductor bodies in which there is a channel region while the diode also includes one or more non-planar semiconductor bodies in which there is a p-type region, an n-type region, or both. One IC stratum may be only hundreds of nanometers in thickness and include both front-side and back-side interconnect levels. The front-side interconnect level is disposed over a front side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the transistor. The back-side interconnect level is disposed over a back side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the semiconductor diode.
1. An integrated circuit (IC), comprising:
a fin transistor structure including one or more first non-planar semiconductor bodies further comprising a channel region having a first conductivity type and a first impurity concentration;
a fin diode structure laterally adjacent to the transistor structure and including one or more second non-planar semiconductor bodies having the first conductivity type and the first impurity concentration, wherein the diode structure further comprises:
a back-side p-type semiconductor in direct contact with a back side of a first end of the second semiconductor bodies; and
a back-side n-type semiconductor in direct contact with the back side of a second end of the second semiconductor bodies;
a front-side interconnect level over a front side of the first semiconductor bodies and coupled to at least one terminal of the fin transistor structure; and
a back-side interconnect level comprising a pair of metal contacts, a first of the pair in direct contact with the back-side p-type semiconductor, and a second of the pair in direct contact with the back-side n-type semiconductor.
2. The IC of claim 1 , wherein:
the transistor structure further comprises:
a source semiconductor and a drain semiconductor separated by the channel region;
a first gate electrode stack including a gate electrode and a gate dielectric over at least a front-side of the channel region; and
the diode structure further comprises a second gate stack over at least a front-side of the second semiconductor bodies, and positioned laterally between the back-side p-type and n-type semiconductor.
3. The IC of claim 1 , wherein an impurity concentration of the back-side p-type semiconductor and of the back-side n-type semiconductor is higher than the first impurity concentration.
4. The IC of claim 1 , wherein the first and second semiconductor bodies, the back-side p-type semiconductor, and back-side n-type semiconductor comprise silicon.
5. The IC of claim 1 , wherein the first and second semiconductor bodies are single crystalline.
6. The IC of claim 5 , wherein the back-side p-type semiconductor and back-side n-type semiconductor are single crystalline.
7. A method of fabricating an integrated circuit (IC), the method comprising:
forming a fin transistor structure including one or more first semiconductor bodies over a substrate, and further comprising a channel region having a first conductivity type and a first impurity concentration;
forming a fin diode structure laterally adjacent to the fin transistor structure, wherein the fin diode structure comprises one or more second non-planar semiconductor bodies having the first conductivity type and the first impurity concentration;
forming a front-side interconnect level over a front side of the fin transistor structure and the fin diode structure, forming the front-side interconnect level further comprising forming a front-side contact coupled to the front-side portion of the second semiconductor bodies;
exposing a back side of at least the second semiconductor bodies by thinning or removing the substrate;
forming a back-side p-type semiconductor in direct contact with the back side of a first end of the second semiconductor bodies;
forming a back-side n-type semiconductor in direct contact with the back side of a second end of the second semiconductor bodies; and
forming a back-side interconnect level in contact with the back-side portion of the second semiconductor bodies, wherein forming the back-side interconnect level comprise forming a pair of metal contacts, a first of the pair in direct contact with the back-side p-type semiconductor, and a second of the pair in direct contact with the back-side n-type semiconductor.
8. The method of claim 7 , wherein forming the front-side contact further comprises forming a pair of metal contacts on either side of an intervening gate stack that is over a portion of the second semiconductor bodies.
9. The method of claim 7 , wherein forming the back-side interconnect level further comprises depositing contact metallization in contact with the back-side p-type semiconductor and with the back-side n-type semiconductor.
10. The method of claim 7 , wherein:
forming the back-side p-type semiconductor further comprises forming the back-side p-type semiconductor with an impurity concentration exceeding the first impurity concentration; and
forming the back-side n-type semiconductor further comprises forming the back-side n-type semiconductor with an impurity concentration exceeding the first impurity concentration.
11. The method of claim 7 , wherein the first and second semiconductor bodies are single crystalline, and wherein forming the back-side p-type semiconductor and forming the back-side n-type semiconductor further comprises epitaxially growing single-crystalline material.
12. The method of claim 7 , wherein forming the back-side p-type semiconductor and forming the back-side n-type semiconductor further comprises forming a material comprising silicon.