Microelectronic devices and electronic systems
A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.
1. A microelectronic device, comprising:
array regions individually comprising:
memory cells comprising access devices and storage node devices;
digit lines coupled to the access devices and extending in a first direction;
word lines coupled to the access devices and extending in a second direction orthogonal to the first direction; and
control logic devices over and in electrical communication with the memory cells;
digit line exit regions horizontally alternating with the array regions in the first direction and individually comprising:
portions of the digit lines extending beyond the array regions adjacent thereto;
digit line contact structures extending through at least some of the portions of the digit lines;
metallic interconnect structures on the digit line contact structures and individually comprising:
a vertical contact region comprising a first portion of a metal material; and
a horizontal pad region overlying the vertical contact region and having greater horizontal dimensions than the vertical contact region, the horizontal pad region comprising:
a first additional portion of the metal material integral and continuous with the first portion of the metal material; and
a first further portion of the metal material overlying and bonded to the first additional portion of the metal material;
contact structures on the metallic interconnect structures; and
routing structures coupled to the contact structures;
word line exit regions horizontally alternating with the array regions in the second direction and individually comprising:
portions of the word lines extending beyond the array regions adjacent thereto;
word line contact structures extending through at least some of the portions of the word lines;
additional metallic interconnect structures on the word line contact structures and individually comprising:
an additional vertical contact region comprising a second portion of the metal material; and
an additional horizontal pad region overlying the additional vertical contact region and having greater horizontal dimensions than the additional vertical contact region, the additional horizontal pad region comprising:
a second additional portion of the metal material integral and continuous with the second portion of the metal material; and
a second further portion of the metal material overlying and bonded to the second additional portion of the metal material;
additional contact structures on the additional metallic interconnect structures; and
additional routing structures coupled to the additional contact structures.
2. The microelectronic device of claim 1 , further comprising:
copper routing structures over and in electrical communication with the routing structures and the additional routing structures; and
aluminum pad structures over and in electrical communication with the copper routing structures.
3. The microelectronic device of claim 1 , wherein the metallic interconnect structures and the additional metallic interconnect structures individually comprise copper.
4. The microelectronic device of claim 3 , wherein the digit line contact structures, the word line contact structures, the contact structures, and the additional contact structures individually comprise one or more of tungsten and titanium nitride.
5. The microelectronic device of claim 1 , further comprising socket regions horizontally offset from the array regions, the digit line exit regions, and the word line exit regions, the socket regions individually comprising deep contact structure assemblies coupling the memory cells to at least some of the control logic devices.
6. The microelectronic device of claim 5 , wherein the socket regions further comprise additional control logic devices having different configurations and operational functions than the control logic devices.
7. The microelectronic device of claim 6 , wherein the socket regions further comprise capacitors coupled to one or more of at least some of the control logic devices and at least some of the additional control logic devices.
8. The microelectronic device of claim 1 , wherein the control logic devices within each array region of the array regions comprise:
sense amplifier devices within multiple sense amplifier regions positioned proximate corners of the array region diagonally opposing one another; and
sub-word line driver devices within multiple sub-word line driver regions positioned proximate additional corners of the array region diagonally opposing one another.
9. The microelectronic device of claim 8 , wherein, for each sense amplifier region of the multiple sense amplifier regions within the array region:
some of the sense amplifier devices within the sense amplifier region are coupled to some of the digit lines extending through the array region; and
some other of the sense amplifier devices within the sense amplifier region are coupled to some of the digit lines extending through an additional one of the array regions neighboring the array region.
10. The microelectronic device of claim 9 , wherein:
the some of the sense amplifier devices are coupled to the some of the digit lines extending through the array region by way of some of the digit line contact structures, some of the metallic interconnect structures, some of the contact structures, and some of the routing structures within one of the digit line exit regions horizontally interposed between the array region and the additional one of the array regions; and
the some other of the sense amplifier devices are coupled to the some of the digit lines horizontally extending through the additional one of the array regions by way of some other of the digit line contact structures, some other of the metallic interconnect structures, some other of the contact structures, and some other of the routing structures within the one of the digit line exit regions.
11. The microelectronic device of claim 8 , wherein, for each sub-word line driver region of the multiple sub-word line driver regions within the array region:
some of the sub-word line driver devices within the sub-word line driver region are coupled to some of the word lines extending through the array region; and
some other of the sub-word line driver devices within the sub-word line driver region are coupled to some of the word lines extending through an additional one of the array regions neighboring the array region.
12. The microelectronic device of claim 11 , wherein:
the some of the sub-word line driver devices are coupled to the some of the word lines extending through the array region by way of some of the word line contact structures, some of the additional metallic interconnect structures, some of the additional contact structures, and some of the additional routing structures within one of the word line exit regions horizontally interposed between the array region and the additional one of the array regions; and
the some other of the sub-word line driver devices are coupled to the some of the word lines extending through the additional one of the array regions by way of some other of the word line contact structures, some other of the additional metallic interconnect structures, some other of the additional contact structures, and some other of the additional routing structures within the one of the word line exit regions.
13. An electronic system, comprising:
an input device;
an output device;
a processor device operably connected to the input device and the output device; and
a memory device operably connected to the processor device and comprising:
memory array regions each comprising dynamic random access memory (DRAM) cells, digit lines coupled to the DRAM cells, word lines coupled to the DRAM cells, and control logic circuitry overlying and in electrical communication with the DRAM cells;
a digit line contact region between two of the memory array regions neighboring one another in a first direction, the digit line contact region comprising:
end portions of some of the digit lines extending past horizontal boundaries of the two of the memory array regions;
digit line contacts coupled to and extending completely through the end portions of the some of the digit lines;
copper interconnects on the digit line contacts and individually comprising:
a vertical contact region comprising a first portion of a copper material; and
a horizontal pad region overlying the vertical contact region and having larger horizontal dimensions than the vertical contact region, the horizontal pad region comprising:
a first additional portion of the copper material integral and continuous with the first portion of the copper material; and
a first further portion of the copper material overlying and bonded to the first additional portion of the copper material;
conductive contacts over and coupled to the copper interconnects; and
conductive routing over and coupled to the conductive contacts; and
a word line contact region between two other of the memory array regions neighboring one another in a second direction perpendicular to the first direction, the word line contact region comprising:
end portions of some of the word lines extending past horizontal boundaries of the two other of the memory array regions;
word line contacts coupled to and extending completely through the end portions of the some of the word lines;
additional copper interconnects on the word line contacts and individually comprising:
an additional vertical contact region comprising a second portion of the copper material; and
an additional horizontal pad region overlying the additional vertical contact region and having larger horizontal dimensions than the additional vertical contact region, the additional horizontal pad region comprising:
a second additional portion of the copper material integral and continuous with the second portion of the copper material; and
a second further portion of the copper material overlying and bonded to the second additional portion of the copper material;
additional conductive contacts over and coupled to the additional copper interconnects; and
additional conductive routing over and coupled to the additional conductive contacts.