Multicore shared cache operation engine
Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.
1. A circuit comprising:
a memory mapped register configured to receive a memory access command;
a buffer coupled to the memory mapped register and configured to store the memory access command;
a trigger control channel configured to receive a trigger event associated with the memory access command and in response to the trigger control channel receiving the trigger event:
obtain the memory access command; and
load the memory access command into a subtiler, wherein the subtiler is configured to translate the memory access command into an instruction associated with a physical memory location; and
a queue configured to receive the instruction and output the instruction to a memory associated with the physical memory location.
2. The circuit of claim 1 , wherein:
the memory access command includes one of a transfer request (TR) command to move data from a source location to a destination location, and a cache request command to send messages to prewarm a specified cache.
3. The circuit of claim 2 , further comprising a packet streaming interface link coupled to the buffer and configured to receive a second memory access command.
4. The circuit of claim 1 , wherein:
the memory mapped register is configured to perform one of a validity check, a channel ownership check, and a fullness check of the buffer.
5. The circuit of claim 2 , wherein:
the TR command is a single 64 byte TR command; and
the memory mapped register includes an atomic submission register configured to receive the TR command and store the TR command in the buffer.
6. The circuit of claim 2 , wherein:
the memory mapped register includes a non-atomic submission register configured to receive the TR command over multiple clock cycles and store the TR command in the buffer.
7. The circuit of claim 1 , wherein:
the trigger event includes one of a local event and a global event; and
the local event is associated with a return status message indicating a result of a previous TR command to the memory access command.
8. The circuit of claim 1 , wherein:
in response to the memory access command exceeding a threshold size, the subtiler is configured to break up the memory access command into a subset of instructions.
9. The circuit of claim 1 , wherein:
the queue includes one of a priority queue and a round robin queue.
10. A circuit comprising:
a plurality of interfaces configured to receive a memory access command, wherein the plurality of interfaces includes a memory mapped register and a packet streaming interface;
a buffer coupled to the plurality of interfaces and configured to store the memory access command;
a trigger control channel configured to receive a trigger event associated with the memory access command, wherein a trigger control channel configuration indicates which of the plurality of interfaces is used to obtain the memory access command, and in response to the trigger control channel receiving the trigger event:
obtain the memory access command; and
load the memory access command into a subtiler, wherein the subtiler is coupled to the buffer and configured to translate the memory access command into an instruction associated with a physical memory location; and
a queue coupled to the subtiler and configured to receive the instruction and output the instruction to a memory associated with the physical memory location.
11. The circuit of claim 10 , wherein the memory mapped register is configured to perform one of a validity check, a channel ownership check, and a fullness check of the buffer.
12. The circuit of claim 10 , wherein the memory mapped register includes an atomic submission register configured to receive a transfer request (TR) command and store the TR command in the buffer.
13. The circuit of claim 12 , wherein the TR command includes a single 64-byte command.
14. The circuit of claim 10 , wherein the memory mapped register includes a non-atomic submission register configured to receive a transfer request (TR) command over multiple clock cycles and store the TR command in the buffer.
15. The circuit of claim 10 , wherein:
the trigger event includes one of a local event and a global event; and
the local event is associated with a return status message indicating a result of a previous TR command to the memory access command.
16. The circuit of claim 10 , wherein in response to the memory access command exceeding a threshold size, the subtiler is configured to break up the memory access command into a subset of instructions.
17. The circuit of claim 10 , wherein the queue includes a priority queue or a round robin queue.