Multi-metal contact structure

1. A method comprising:

providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;

disposing a first conductive material having a first melting point within the recess or opening and forming a first portion of an interconnect structure of the substrate; and

disposing a second conductive material having a second melting point different from the first melting point within the recess or opening and at least partially surrounded by the first conductive material, the second conductive material forming a second portion of the interconnect structure of the substrate, the second portion of the interconnect structure comprising a plurality of conductive portions extending normal to the plane of the substrate; and

providing a barrier layer between the substrate and the first conductive material.

2. The method of claim I, further comprising disposing a layer of the first conductive material over an exposed surface of the second portion of the interconnect structure.

3. The method of claim 1 , further comprising disposing a layer of a third conductive material, different from the first and second conductive materials over an exposed surface of the first and second portions of the interconnect structure.

4. The method of claim I. further comprising disposing one or more additional conductive materials having one or more additional melting points different from the first melting point and the second melting point within the recess or opening and forming one or more additional portions of the interconnect structure of the substrate.

5. The method of claim 1 , further comprising disposing the first portion of the interconnect structure and the second portion of the interconnect structure as adjacent vertical layers, extending normal to a plane of the first surface of the substrate.

6. The method of claim 5 , further comprising disposing an adhesion layer comprising at least one of titanium, tantalum, or chromium within the recess or opening prior to disposing the adjacent vertical layers.

7. The method of claim 1 , wherein the substrate is a first substrate and the interconnect structure is a first interconnect structure, and further comprising bonding a second interconnect structure of a second substrate to the first interconnect structure by at least one of a direct bond of an insulator material to another insulator material without an adhesive or by a metal to metal diffusion bond, thereby forming one of an electrical contact pad or a via.

8. The method of claim 1 , wherein a coefficient of thermal expansion (CTE) of the first conductive material is different from a CTE of the second conductive material.

9. A method, comprising:

providing a microelectronic component comprising:

providing a first substrate having a recess or opening extending from a first surface of the first substrate, at least a portion of the first surface of the first substrate having a planarized topography;

disposing a first conductive material having a first melting point within the recess or opening, extending normal to a plane of the first substrate and forming a first portion of a first interconnect structure of the microelectronic component;

disposing a second conductive material having a second melting point different from the first melting point within the recess or opening, extending normal to the plane of the first substrate and forming a second portion of the first interconnect structure of the microelectronic component, the second portion of the first interconnect structure comprising a plurality of conductive portions at least partially surrounded by the first conductive material; and

bonding a second interconnect structure of a second substrate to the first interconnect structure by at least one of a direct bond of an insulator material to another insulator material without an adhesive or by a metal to metal diffusion bond, thereby forming one of an electrical contact pad or a via with the first interconnect structure and the second interconnect structure.

10. The method of claim 9 , further comprising disposing one or more additional conductive materials having one or more additional melting points different from the first melting point and the second melting point within the recess or opening of the first substrate and forming one or more additional portions of the first interconnect structure of the first substrate.

11. The method of claim 10 , furthercomprising:

providing a recess or opening extending from a first surface of the second substrate of the microelectronic component, at least a portion of the first surface of the second substrate having a planarized topography;

disposing a third conductive material having a third melting point within the recess or opening of the second substrate, extending normal to a plane of the second substrate and forming a first portion of the second interconnect structure; and

disposing a fourth conductive material having a fourth melting point different from the third melting point within the recess or opening of the second substrate, extending normal to the plane of the second substrate and contacting the first portion of the second interconnect structure and forming a second portion of the second interconnect structure.

12. The method of claim 11 , further comprising disposing one or more additional conductive materials having one or more additional melting points different from the third melting point and the fourth melting point within the recess or opening of the second substrate and forming one or more additional portions of the second interconnect structure of the second substrate.

13. A method comprising:

providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;

disposing a first conductive material having a first coefficient of thermal expansion (CTE) within the recess or opening and forming a first portion of an interconnect structure, the first portion of the interconnect structure extending normal to a plane of the substrate;

disposing a second conductive material having a second CTE different from the first CTE within the recess or opening, the second conductive material forming a second portion of the interconnect structure, the second portion of the interconnect structure comprising a plurality of conductive portions extending normal to the plane of the substrate, the first conductive material at least partially surrounding the second conductive material; and

disposing a barrier layer between the substrate and the first conductive material.

14. The method of claim 13 , further comprising disposing one or more additional conductive materials having one or more additional coefficients of thermal expansion different from the first CTE and the second CTE within the recess or opening and forming one or more additional portions of the interconnect structure.

15. The method of claim 13 , wherein the substrate is a first substrate and the interconnect structure is a first interconnect structure, and further comprising bonding a second interconnect structure of a second substrate to the first interconnect structure by at least one of a direct bond of an insulator material to another insulator material without an adhesive or by a metal to metal diffusion bond, thereby forming one of an electrical contact pad or a via.

16. A method of fabricating a microelectronic component comprising:

forming a recess or opening in a surface of a substrate;

disposing a first conductive material having a first coefficient of theuiial expansion (CTE) within the recess or opening, the first conductive material at least partially filling the recess or opening and forming a first portion of an interconnect structure of the microelectronic component;

disposing a second conductive material having a second CTE different from the first CTE within the recess or opening and forming a second portion of the interconnect structure of the microelectronic component; and

planarizing the surface of the substrate, the first conductive material, and the second. conductive material and forming a planar bonding surface comprising the first portion and the second portion of the interconnect stricture and a planar dielectric surface.

17. The method of claim 16 , further comprising forming one of an electrical contact pad or a via from the first portion and the second portion of the interconnect structure.

18. The method of claim 16 further comprising mechanically coupling the planar bonding surface to a surface of a second substrate.

19. The method of claim 18 , further comprising directly bonding the planar bonding surface to the surface of the second substrate without an adhesive.

20. The method of claim 16 , further comprising forming a barrier layer or adhesive layer within the recess or opening before disposing the first conductive material.