Flipped gate voltage reference and method of using
View Patent ↗A voltage reference includes a first current source and a flipped gate transistor coupled in series between an operating voltage node and a negative supply voltage node, a first transistor and a second current source coupled in series between the operating voltage node and the negative supply voltage node, and an output node between the first transistor and the second current source. A gate of the first transistor is coupled to a gate of the flipped gate transistor, the output node is configured to output a reference voltage, the first current source is configured to provide a first current to the flipped gate transistor, the second current source is configured to provide a second current to the first transistor, the second current being less than the first current, and the first transistor has a size greater than a size of the flipped gate transistor.
1. A voltage reference comprising:
a first current source and a flipped gate transistor coupled in series between an operating voltage node and a negative supply voltage node;
a first transistor and a second current source coupled in series between the operating voltage node and the negative supply voltage node, wherein
a gate of the first transistor is coupled to a gate of the flipped gate transistor, and
the second current source is connected between the first transistor and the negative supply voltage node; and
an output node between the first transistor and the second current source, the output node configured to output a reference voltage,
wherein
the first current source is configured to provide a first current to the flipped gate transistor,
the second current source is configured to provide a second current to the first transistor, the second current being less than the first current, and
the first transistor has a size greater than a size of the flipped gate transistor.
2. The voltage reference of claim 1 , wherein
the voltage reference comprises a semiconductor-based material,
the first and second current sources are configured to provide the first and second currents relative to the sizes of the flipped gate and first transistors so as to generate a predetermined difference between a gate-source voltage of the flipped gate transistor and a gate-source voltage of the first transistor, and
the predetermined difference is approximately equal to a bandgap voltage of the semiconductor-based material.
3. The voltage reference of claim 1 , wherein
the first current source comprises a current mirror comprising a parallel arrangement of mirror transistors in series with mirror resistors,
each mirror transistor has a size based on an integer multiple of a unit transistor size, and
each mirror resistor comprises a series of one or more unit resistor arrangements.
4. The voltage reference of claim 3 , wherein
the voltage reference further comprises a bias current generator, and
the current mirror is configured to provide the first current based on a bias current received from the bias current generator.
5. The voltage reference of claim 3 , wherein the current mirror is configured to provide the first current based on a bias current received from an external supply.
6. The voltage reference of claim 1 , wherein
the second current source comprises a current mirror comprising a parallel arrangement of mirror transistors in series with mirror resistors,
each mirror transistor has a size based on an integer multiple of a unit transistor size, and
each mirror resistor comprises a series of one or more unit resistor arrangements.
7. The voltage reference of claim 6 , wherein the current mirror is configured to provide the second current based on a third current received from the first current source.
8. The voltage reference of claim 1 , further comprising:
a boxing circuit coupled between the operating voltage node and the output node; and
a second transistor coupled between the output node and the negative supply voltage node,
wherein
a size of the second transistor is approximately equal to a size of the first transistor, and
the boxing circuit is configured to maintain a voltage drop across the first transistor approximately equal to the reference voltage.
9. A voltage reference comprising:
a first mirror resistor, a first mirror transistor, and a flipped gate transistor coupled in series between an operating voltage node and a negative supply voltage node;
a first transistor, a second mirror transistor, and a second mirror resistor coupled in series between the operating voltage node and the negative supply voltage node, wherein a gate of the first transistor is coupled to a gate of the flipped gate transistor; and
an output node between the first transistor and the second mirror transistor, the output node configured to output a reference voltage,
wherein
the first mirror resistor and first mirror transistor are configured to provide a first current to the flipped gate transistor,
the second mirror transistor and second mirror resistor are configured to provide a second current to the first transistor, the second current being less than the first current, and
a size of the first transistor is a first integer multiple of a size of the flipped gate transistor.
10. The voltage reference of claim 9 , wherein the first integer multiple has a value ranging from 2 to 50.
11. The voltage reference of claim 9 , wherein
the voltage reference comprises a semiconductor-based material,
the first and second currents have values relative to each other and to the first integer multiple configured to generate a predetermined difference between a gate-source voltage of the flipped gate transistor and a gate-source voltage of the first transistor, and
the predetermined difference is approximately equal to a bandgap voltage of the semiconductor-based material.
12. The voltage reference of claim 9 , wherein
a size of the first mirror transistor is based on a second integer multiple of a first unit transistor size, and
a size of the second mirror transistor is based on a third integer multiple of a second unit transistor size.
13. The voltage reference of claim 9 , wherein each of the first and second mirror resistors comprises a series of one or more unit resistor arrangements.
14. The voltage reference of claim 9 , further comprising a third mirror resistor and a third mirror transistor coupled in series between the operating voltage node and the negative supply voltage node, wherein
a gate of the first mirror transistor is coupled to a gate of the third mirror transistor, and
the gates of the first and third mirror transistors are coupled to a bias current generator or to an external supply.
15. The voltage reference of claim 9 , further comprising third and fourth mirror resistors and third and fourth mirror transistors coupled in series between the operating voltage node and the negative supply voltage node, wherein
a gate of the first mirror transistor is coupled with a gate of the third mirror transistor, and
a gate of the second mirror transistor is coupled to a gate of the fourth mirror transistor.
16. The voltage reference of claim 9 , further comprising:
a boxing circuit coupled between the operating voltage node and the first transistor; and
a second transistor arranged in parallel with the second mirror transistor and the second mirror resistor,
wherein
a size of the second transistor is approximately equal to a size of the first transistor, and
the boxing circuit is configured to maintain a voltage drop across the first transistor approximately equal to the reference voltage.
17. A method of using a voltage reference, the method comprising:
generating a first current through a flipped gate transistor;
generating a second current through a first transistor using a current source connected between the first transistor and a negative supply voltage node, the first transistor having a gate coupled to a gate of the flipped gate transistor and a size greater than a size of the flipped gate transistor; and
outputting a reference voltage at a source of the first transistor, the reference voltage being based on the first current being greater than the second current.
18. The method of claim 17 , wherein the reference voltage being based on the first current being greater than the second current comprises the first and second currents having values relative to each other and to the sizes of the flipped gate transistor and the first transistor configured to cause the reference voltage to have a value approximately equal to a bandgap voltage of a semiconductor-based material of the voltage reference.
19. The method of claim 17 , wherein the generating the first current comprises mirroring a bias current received from a bias current generator or an external supply.
20. The method of claim 17 , wherein each of the generating the first current and the generating the second current comprises using a mirror transistor to control a current through a series of one or more unit resistor arrangements.