Stacked memory chip solution with reduced package inputs/outputs (I/Os)
A stack of memory chips and a logic chip is placed within a same package. Multiple memory chips of the stack of memory chips are divided into fractions, and multiple internal channels within the package that emanate from the logic chip are coupled to respective ones of the fractions. The logic chip has a multiplexer, including a multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.
1. An apparatus, comprising:
a logic chip upon which a stack of memory chips is to be placed, the stack of memory chips and the logic chip to be placed within a same package, wherein multiple memory chips of the stack of memory chips are divided into fractions;
multiple internal channels within the same package that emanate from the logic chip to be coupled to respective ones of the fractions; and
the logic chip comprising:
a multiplexer, the multiplexer to multiplex a single input/output (I/O) channel of the same package to the multiple internal channels, and
a second multiplexer, the second multiplexer to multiplex other multiple internal channels within the same package coupled to other ones of the fractions to another single I/O channel of the same package.
2. The apparatus of claim 1 wherein the stack of memory chips is to comprise one of:
4 memory chips total;
8 memory chips total;
12 memory chips total.
3. The apparatus of claim 1 wherein the fractions comprise one of:
halves;
quarters.
4. The apparatus of claim 1 wherein the multiplexer and second multiplexer each have a multiplexing ratio of one of:
1:4;
1:8.
5. The apparatus of claim 1 wherein the multiplexer has a multiplexing ratio of one of:
1:4;
1:8.
6. The apparatus of claim 1 wherein a particular one of the multiple internal channels is to be coupled to more than one of the fractions.
7. A computing system comprising:
a package containing a stack of memory chips mounted on a logic chip, multiple memory chips of the stack of memory chips divided into fractions, multiple internal channels within the package coupled to respective ones of the fractions, the logic chip comprising:
a multiplexer, the multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels, the package mounted to a printed circuit board, and
a second multiplexer, the second multiplexer to multiplex other internal respective channels of other multiples ones of the fractions to another single output channel of the package; and
a host chip mounted to a printed circuit board, wherein, the single I/O channel of the package is coupled to the host chip through wiring formed within the printed circuit board and not with wiring formed in a semiconductor chip that is embedded within the printed circuit board.
8. The computing system of claim 7 wherein the stack of memory chips comprises one of:
4 memory chips total;
8 memory chips total;
12 memory chips total.
9. The computing system of claim 7 wherein the fractions comprise one of:
halves;
quarters.
10. The computing system of claim 7 wherein the multiplexer and second multiplexer each have a multiplexing ratio of one of:
1:4;
1:8.
11. The computing system of claim 7 wherein the multiplexer has a multiplexing ratio of one of:
1:4;
1:8.
12. The computing system of claim 7 wherein a particular one of the multiple internal channels is coupled to more than one of the fractions.
13. The computing system of claim 7 wherein the host chip is a processor chip.
14. A memory module tile, comprising:
a) a package containing a stack of memory chips mounted on a logic chip, multiple memory chips of the stack of memory chips divided into fractions, multiple internal channels within the package coupled to respective ones of the fractions, the logic chip comprising a multiplexer, the multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels, the package mounted to a printed circuit board; and,
b) a buffer chip mounted to a printed circuit board, wherein, the single I/O channel of the package is coupled to the buffer chip through wiring formed within the printed circuit board and not with wiring formed in a semiconductor chip that is embedded within the printed circuit board;
c) a link transmitter/receiver, the link transmitter/receiver to couple to a link that is coupled to a processor on an opposite end of the link.
15. The memory module tile of claim 14 wherein the link transmitter/receiver is an opto-electronic transmitter/receiver.
16. The memory module tile of claim 14 wherein the stack of memory chips comprises one of:
4 memory chips total;
8 memory chips total;
12 memory chips total.
17. The memory module tile of claim 14 wherein the fractions comprise one of:
halves;
quarters.
18. The memory module tile of claim 14 wherein the logic chip comprises a second multiplexer, the second multiplexer to multiplex other internal respective channels of other multiples ones of the fractions to another single output channel of the package.
19. An apparatus, comprising:
a stack of memory chips upon a logic chip, the stack of memory chips and the logic chip within a package, multiple memory chips of the stack of memory chips divided into fractions of at least quarters, multiple internal channels within the package coupled to respective ones of the fractions, wherein a width of a respective one of the multiple internal channels is less than 64b and each of the multiple memory chips have a respective capacity of at least 16 Gb; and
the logic chip comprising:
a multiplexer, the multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels, and
a second multiplexer, the second multiplexer to multiplex other multiple internal channels within the package coupled to other ones of the fractions to another single I/O channel of the package.