Semiconductor interconnect structure with bottom self-aligned via landing
View Patent ↗A semiconductor structure and method for forming a semiconductor structure includes formation of a recess in a metal layer during the fabrication process to provide process improvements and a conductive via with reduced contact resistance. The semiconductor structure includes a dielectric layer, a metal layer, an etch stop layer, and a conductive via. The top surface of the dielectric layer extends above a top surface of the metal layer, and a bottom surface of the conductive via extends below the top surface of the dielectric layer.
1. A semiconductor structure, comprising:
a first dielectric layer;
a metal layer formed adjacent the first dielectric layer;
a contact contacting a bottom surface of the metal layer;
an etch stop layer formed on a top surface of the first dielectric layer and on a top surface of the metal layer, the etch stop layer extending over an entirety of a top surface of a first portion of the first dielectric layer and only partially extending over a top surface of a second portion of the first dielectric layer, the first and second portions of the first dielectric layer being separated by the metal layer; and
a second dielectric layer including a first portion over a top surface of the etch stop layer and a second portion along sidewalls of the first dielectric layer,
wherein the second dielectric layer is a single, continuous layer extending from the first portion to the second portion, and
wherein the top surface of the first dielectric layer extends above the top surface of the metal layer.
2. The semiconductor structure of claim 1 , further comprising a conductive via formed adjacent the first dielectric layer and the metal layer, wherein a bottom surface of the conductive via extends below the top surface of the first dielectric layer.
3. The semiconductor structure of claim 2 , further comprising a second metal layer over and electrically connected to the conductive via.
4. The semiconductor structure of claim 1 , wherein the top surface of the first dielectric layer extends above the top surface of the metal layer by a magnitude ranging from 2 nanometers to 10 nanometers.
5. The semiconductor structure of claim 1 , wherein the etch stop layer includes aluminum oxide.
6. The semiconductor structure of claim 1 , wherein a thickness of the etch stop layer ranges from 1 nanometer to 15 nanometers.
7. The semiconductor structure of claim 1 , wherein the second dielectric layer is surrounded by a bottom surface and sidewall surfaces of the etch stop layer.
8. The semiconductor structure of claim 1 , wherein the first metal layer directly contacts the contact.
9. A semiconductor structure, comprising:
a first dielectric layer;
a first metal layer formed adjacent the first dielectric layer;
a conductive via formed adjacent the first metal layer such that a bottom surface of the conductive via is adjacent a top surface of the first metal layer, a bottom portion of the conductive via directly contacting sidewalls of the first dielectric layer and a top surface of the first metal layer;
a second metal layer formed in the conductive via; and
a second dielectric layer formed over the first metal layer, wherein a first portion of the second dielectric layer extends along sidewalls of the first dielectric layer and a second portion of the second dielectric layer extends along sidewalls of the second metal layer, the second dielectric layer extending from the first portion to the second portion as a single, continuous layer,
wherein a bottom surface of the second metal layer extends below a top surface of the first dielectric layer, and
wherein a top surface of the second metal layer extends above the second dielectric layer.
10. The semiconductor structure of claim 9 , wherein the top surface of the first dielectric layer extends above the top surface of the first metal layer.
11. The semiconductor structure of claim 9 , further comprising an etch stop layer formed on the top surface of the first dielectric layer and the first metal layer, wherein the etch stop layer is formed using aluminum oxide and a thickness of the etch stop layer ranges from 1 nanometer to 15 nanometers.
12. The semiconductor structure of claim 9 , wherein the bottom surface of the second metal layer extends below the top surface of the first dielectric layer by a magnitude ranging from 2 nanometers to 10 nanometers.
13. The semiconductor structure of claim 9 , further comprising contacts contacting the first metal layer.
14. A semiconductor structure, comprising:
a first dielectric layer;
a first metal layer formed adjacent the first dielectric layer;
a contact contacting a bottom surface of the first metal layer;
a second metal layer contacting top regions of the first metal layer;
an etch stop layer formed on a top surface of the first dielectric layer and on a top surface of the first metal layer, the etch stop layer including a first portion that fully covers a top surface of a first portion of the first dielectric layer and a second portion that only partially covers a top surface of a second portion of the first dielectric layer, the first and second portions of the first dielectric layer being separated by the first metal layer; and
a second dielectric layer over the first metal layer, the second dielectric layer including a first portion over a top surface of the etch stop layer and a second portion below the top surface of the etch stop layer, the second dielectric layer extending from the first portion to the second portion as a single, continuous layer,
wherein a bottom surface of the second dielectric layer extends below the top surface of the first dielectric layer,
wherein the top surface of the first dielectric layer extends above the top surface of the first metal layer.
15. The semiconductor structure of claim 14 , wherein the top surface of the first dielectric layer extends above the top surface of the first metal layer by a magnitude ranging from 2 nanometers to 10 nanometers.
16. The semiconductor structure of claim 14 , wherein the etch stop layer includes aluminum oxide.
17. The semiconductor structure of claim 14 , wherein a thickness of the etch stop layer ranges from 1 nanometer to 15 nanometers.
18. The semiconductor structure of claim 14 , wherein the second portion of the second dielectric layer is surrounded by a bottom surface and sidewall surfaces of the etch stop layer.
19. The semiconductor structure of claim 14 , further comprising a conductive via formed adjacent the first metal layer such that a bottom surface of the conductive via directly contacts the first metal layer.
20. The semiconductor structure of claim 19 , further comprising a second metal layer formed over and electrically connected to the conductive via.