IP Library Granted Patent US 11,804,426
Granted Patent B2
US 11,804,426 · App. 17/379,724 · Granted Oct 31, 2023

Integrated circuit structures in package substrates

Inventors: Sanka Ganesan (Chandler, AZ); William James Lambert (Chandler, AZ); Zhichao Zhang (Chandler, AZ); Sri Chaitra Jyotsna Chavali (Chandler, AZ); Stephen Andrew Smith (Laveen, AZ); Michael James Hill (Gilbert, AZ); Zhenguo Jiang (Chandler, AZ)
Assignee: Intel Corporation
H01L23/49816H01L21/4832H01L21/4853H01L21/568H01L23/3107H01L24/73H01L25/0657H01L25/105H05K1/181H05K7/023
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Quick Facts
Patent No.
US 11,804,426
App. No.
17/379,724
Granted
Oct 31, 2023
Kind
B2
Abstract

Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Claims (19)

1. An integrated circuit (IC) package, comprising:

a package substrate; and

a die coupled to the package substrate;

wherein the package substrate includes a shield structure, wherein the shield structure includes at least two vias and at least two pads arranged to provide solid walls of conductive material proximate to edges of the package substrate, the vias surrounded on their sides by a dielectric material, and the solid walls of conductive material providing a conductive sleeve around an interior portion of the package substrate.

2. The IC package of claim 1 , wherein one of the pads of the shield structure includes a metal plane having at least one opening.

3. The IC package of claim 2 , wherein an opening in the metal plane is located under the die.

4. The IC package of claim 2 , wherein the metal plane is coplanar with conductive contacts of the package substrate, and the die is coupled to the conductive contacts by interconnects that include solder.

5. The IC package of claim 1 , wherein the shield structure provides a hermetic seal at edges of the package substrate.

6. The IC package of claim 1 , further comprising:

a metal layer on the die, wherein the die is between the metal layer and the package substrate.

7. The IC package of claim 6 , wherein the metal layer does not extend onto side faces of the die.

8. The IC package of claim 1 , further comprising:

a metal layer at side faces of the die.

9. The IC package of claim 1 , further comprising:

a metal layer shielding interconnects between the die and the package substrate.

10. The IC package of claim 1 , further comprising:

a mold material above the die and the package substrate.

11. The IC package of claim 1 , wherein the shield structure is coupled to a ground.

12. The IC package of claim 1 , wherein the die is not electrically coupled to the shield structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072549/0402 →
Continuity (3)
Continuation 16855629 · Apr 22, 2020
Continuation 15944728 · Apr 3, 2018
Related Publication 20210351116A1 · Nov 11, 2021