IP Library › Granted Patent US 11,579,539
Granted Patent B2
US 11,579,539 · App. 17/380,633 · Granted Feb 14, 2023

Method and apparatus for improving critical dimension variation

Inventors: Ming-Hsun Lin (Hsinchu, TW); Yu-Hsiang Ho (Hsinchu, TW); Jhun Hua Chen (Changhua, TW); Chi-Hung Liao (Sanchong, TW); Teng Kuei Chuang (Taichung, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
G03F7/7085G03F7/70558G03F7/70925
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Quick Facts
Patent No.
US 11,579,539
App. No.
17/380,633
Granted
Feb 14, 2023
Kind
B2
Abstract

A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.

Claims (40)

1. A method, comprising:

obtaining a relationship between thicknesses of a contamination layer formed on a mask and amounts of compensation energy to remove the contamination layer;

obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device; and

removing the first contamination layer by applying first amounts of compensation energy calculated from the relationship to a first light directed to the mask, wherein each amount of compensation energy of the first amounts of compensation energy is less than a previous amount of compensation energy of the first amounts of compensation energy.

2. The method of claim 1 , further comprising measuring the first thickness of the first contamination layer by the thickness measuring device.

3. The method of claim 2 , wherein the measuring the first thickness of the first contamination layer is performed in a processing apparatus.

4. The method of claim 2 , wherein the measuring the first thickness of the first contamination layer is performed in a mask storage.

5. The method of claim 1 , further comprising forming a second contamination layer on the mask after applying the first amounts of compensation energy, wherein the second contamination layer is formed while the mask is idle for a period of time.

6. The method of claim 5 , wherein the period of time is greater than about eight hours.

7. The method of claim 5 , wherein the mask is disposed in a lithography system while being idle.

8. The method of claim 7 , further comprising applying second amounts of compensation energy calculated from the relationship to a second light directed to the mask.

9. The method of claim 8 , wherein the second contamination layer is removed by the second amounts of compensation energy.

10. A lithography process, comprising:

performing the lithography process in a lithography system, the lithography system comprising:

a first light source;

a mask stage;

a substrate stage;

a thickness measuring device configured to measure a thickness of a contamination layer formed on a mask to be disposed on the mask stage; and

a controller configured to control the first light source to emit a light with gradually decreasing amounts of compensation energy to remove the contamination layer while performing the lithography process.

11. The lithography process of claim 10 , wherein the thickness measuring device comprises a second light source and a detector.

12. The lithography process of claim 11 , further comprising:

an illuminator disposed between the first light source and the mask stage; and

a projection optics box disposed between the mask stage and the substrate stage.

13. The lithography process of claim 10 , wherein the mask stage and the substrate stage are disposed in a lithography chamber, and the first light source and the thickness measuring device are disposed in a device chamber adjacent the lithography chamber.

14. The lithography process of claim 13 , further comprising a transferring module and a transportation stage, wherein the transportation stage is disposed between the transferring module and the lithography chamber.

15. The lithography process of claim 13 , further comprising a shaft coupled to the mask stage, wherein the shaft is configured to tilt the mask stage with respect to a plane substantially parallel to a top surface of the substrate stage.

16. The lithography process of claim 10 , wherein the lithography process is an extreme ultraviolet lithography process.

17. A lithography system, comprising:

a light source configured to expose a photoresist layer;

a mask stage;

a substrate stage;

a mask storage, comprising:

a plurality of storage units; and

a first thickness measuring device configured to measure a thickness of a contamination layer formed on a mask to be disposed in the mask storage; and

a controller configured to control the light source to emit a light with gradually decreasing amounts of compensation energy to remove the contamination layer.

18. The lithography system of claim 17 , further comprising:

an illuminator disposed between the light source and the mask stage; and

a projection optics box disposed between the mask stage and the substrate stage.

19. The lithography system of claim 18 , wherein the mask stage and the substrate stage are disposed in a lithography chamber, and the light source is disposed in a device chamber adjacent the lithography chamber.

20. The lithography system of claim 19 , further comprising a second thickness measuring device disposed in the device chamber, wherein the second thickness measuring device is electrically connected to the controller.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2021
From: LIN, MING-HSUN; HO, YU-HSIANG; CHEN, JHUN HUA; LIAO, CHI-HUNG; CHUANG, TENG KUEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 056917/0763 →
Continuity (2)
Provisional Application 63156016 · Mar 3, 2021
Related Publication 20220283508A1 · Sep 8, 2022
Cited By (1)
US 12,379,674