IP Library › Granted Patent US 12,379,674
Granted Patent B2
US 12,379,674 · App. 18/646,813 · Granted Aug 5, 2025

Method and apparatus for improving critical dimension variation

Inventors: Ming-Hsun Lin (Hsinchu, TW); Yu-Hsiang Ho (Taichung, TW); Chi-Hung Liao (New Taipei, TW); Teng Kuei Chuang (Taichung, TW); Jhun Hua Chen (Changhua, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
G03F7/7085G03F7/70558G03F7/70925
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Quick Facts
Patent No.
US 12,379,674
App. No.
18/646,813
Granted
Aug 5, 2025
Kind
B2
Abstract

A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.

Claims (41)

1. A method, comprising:

performing a first lithography process using a mask in a lithography system;

idling the mask for a period of time, wherein a contamination layer is formed on the mask;

measuring a thickness of the contamination layer formed on the mask; and

performing a plurality of second lithography processes using the mask having the contamination layer, comprising:

directing a first light from a first light source to the mask and a first substrate, wherein the first light has a first energy;

directing the first light to the mask and a second substrate, wherein the first light has a second energy substantially less than the first energy;

directing the first light to the mask and a third substrate, wherein the first light has a third energy substantially less than the second energy, and the contamination layer is removed;

directing the first light to the mask and a fourth substrate, wherein the first light has a fourth energy substantially less than the third energy; and

directing the first light to the mask and a fifth substrate, wherein the first light has the fourth energy.

2. The method of claim 1 , wherein the thickness of the contamination layer is measured by directing a second light from a second light source to the mask.

3. The method of claim 1 , wherein the measuring of the thickness of the contamination layer is performed in the lithography system.

4. The method of claim 1 , wherein the measuring of the thickness of the contamination layer is performed in a mask storage.

5. The method of claim 1 , wherein the period of time is greater than about eight hours.

6. The method of claim 5 , wherein the mask is disposed in the lithography system while being idle.

7. The method of claim 1 , wherein the first lithography process comprises:

directing the first light to the mask and a sixth substrate, wherein the first light has the fourth energy.

8. A lithography process, comprising:

directing a first light from a first light source to a mask, wherein the first light is configured to pattern a substrate;

measuring a thickness of a first contamination layer formed on the mask; and

adding a compensation energy multiple times to the first light to remove the first contamination layer, wherein each time an amount of the compensation energy is less than an amount of the compensation energy in the previous time.

9. The lithography process of claim 8 , wherein the compensation energy is determined from a relationship between thicknesses of a second contamination layer and amounts of compensation energy to remove the second contamination layer.

10. The lithography process of claim 9 , wherein the removing of the first contamination layer increases a critical dimension of a pattern formed in the substrate.

11. The lithography process of claim 10 , wherein the thickness is measured by directing a second light from a second light source to the mask and reflecting the second light from the mask to a detector.

12. The lithography process of claim 10 , further comprising reflecting the first light from the mask to a projection optics module.

13. The lithography process of claim 12 , further comprising directing the first light to an illuminator prior to directing the first light to the mask.

14. The lithography process of claim 13 , wherein the illuminator comprises mirrors that are switchable to reflect the first light to different illumination positions.

15. The lithography process of claim 10 , wherein the first light is an extreme ultraviolet light.

16. The lithography process of claim 15 , wherein the lithography process is an extreme ultraviolet lithography process.

17. A lithography system, comprising:

a light source configured to expose a photoresist layer;

a mask stage;

a mask disposed on the mask stage;

a substrate stage;

a thickness measuring device configured to measure a thickness of a contamination layer formed on the mask; and

a controller configured to collect data from the thickness measuring device and to control the light source to emit a light with gradually decreasing amounts of compensation energy to remove the contamination layer based on the data from the thickness measuring device.

18. The lithography system of claim 17 , further comprising:

an illuminator disposed between the light source and the mask stage; and

a projection optics box disposed between the mask stage and the substrate stage.

19. The lithography system of claim 17 , wherein the mask stage and the substrate stage are disposed in a lithography chamber, and the light source is disposed in a device chamber adjacent the lithography chamber.

20. The lithography system of claim 17 , further comprising a mask storage, wherein the thickness measuring device is disposed in the mask storage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2024
From: LIN, MING-HSUN; HO, YU-HSIANG; LIAO, CHI-HUNG; CHUANG, TENG KUEI; CHEN, JHUN HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 067232/0084 →
Continuity (4)
Continuation 18109183 · Feb 13, 2023
Continuation 17380633 · Jul 20, 2021
Provisional Application 63156016 · Mar 3, 2021
Related Publication 20240295831A1 · Sep 5, 2024
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