Non-volatile memory controller device and non-volatile memory device

1. A non-volatile memory controlling device configured to connect a non-volatile memory module and a host including a processor and a host memory, the device comprising:

a first doorbell region that is exposed to a configuration space of a host interface connecting with the host and is updated when the host issues an input/output (I/O) request command to the host memory;

a fetch managing module that fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated;

a data transferring module that checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module;

a completion handling module that writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request; and

a second doorbell region that is exposed to the configuration space and is updated when the I/O service is terminated by the host;

wherein the request information includes a logical address and a host memory address indicating a location of the host memory, and

wherein the data transferring module includes

a first engine that sets a source address and a destination address for the data transferring module based on the logical address and the host memory address, and

a second engine that performs the transfer of the target data based on the source address and the destination address.

2. The device of claim 1 , wherein the first doorbell region, the fetch managing module, the data transferring module, the completion handling module, and the second doorbell region are implemented as hardware.

3. The device of claim 1 , wherein the first doorbell region, the fetch managing module, the data transferring module, the completion handling module, and the second doorbell region are implemented as the hardware at a register transfer level (RTL).

4. The device of claim 1 , wherein the first doorbell region, the fetch managing module, the data transferring module, the completion handling module, and the second doorbell region are connected by an internal memory bus of the non-volatile memory controlling device.

5. The device of claim 4 , wherein the internal memory bus includes an advanced extensible interface (AXI) bus.

6. The device of claim 4 , wherein the first doorbell region and the second doorbell region are mapped an address space of the internal memory bus.

7. The device of claim 1 , wherein the host interface includes a peripheral component interconnect express (PCIe) interface, and

wherein the configuration space includes base address registers (BARs).

8. The device of claim 1 , wherein the fetch managing module parses the request information from the command.

9. The device of claim 1 , wherein the second engine includes a direct memory access (DMA) engine.

10. The device of claim 1 , wherein the host memory address includes a physical region page (PRP).

11. The device of claim 10 , wherein the first engine brings a PRP list from the host memory based on the PRP,

wherein the PRP list includes at least one PRP entry indicating a location of the host memory, and

wherein the first engine detects the location of the host memory indicated by the PRP entry.

12. The device of claim 1 , wherein the non-volatile memory controlling device is connected to the non-volatile memory module through a plurality of channels, and

wherein the second engine includes a plurality of DMA cores that correspond to the plurality of channels, respectively.

13. The device of claim 12 , wherein the second engine splits the target data for the I/O request into a plurality of data chunks and spreads the data chunks across the plurality of DMA cores.

14. The device of claim 1 , wherein a plurality of queue pairs exist in the host memory,

wherein each of the queue pairs includes a pair of submission queue (SQ) and competition queue (CQ), and

wherein the fetch managing module fetches the command from the SQ of the queue pair corresponding to an entry updated in the first doorbell region among the plurality of queue pairs.

15. The device of claim 14 , wherein the completion handling module detects the CQ corresponding to the SQ from which the command is fetched based on information forwarded from the fetch managing module.

16. A non-volatile memory device configured to be connected to a host including a processor and a host memory, the device comprising:

a non-volatile memory module;

a first doorbell region that is exposed to a configuration space of a host interface connecting with the host and is updated when the host issues an input/output (I/O) request command to the host memory;

a fetch managing module that fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated;

a data transferring module that checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module;

a completion handling module that writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request; and

a second doorbell region that is exposed to the configuration space and is updated when the I/O service is terminated by the host;

wherein the request information includes a logical address and a host memory address indicating a location of the host memory, and

wherein the data transferring module includes

a first engine that sets a source address and a destination address for the data transferring module based on the logical address and the host memory address, and

a second engine that performs the transfer of the target data based on the source address and the destination address.