Scatter and gather streaming data through a circular FIFO
Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.
1 . An apparatus, comprising:
a buffer to store data from a plurality of producer direct memory access (DMA) engines comprising a first producer DMA engine and second producer DMA engine;
the first producer DMA engine respectively comprising circuitry configured to:
store a respective first portion of data to a respective first location in the buffer; and
send, upon completion of the storing of the first portion of data, a first write pointer identifying the respective first location to indicate the respective first portion of the data is ready to be consumed;
the second producer DMA engine comprising circuitry configured to:
store a second portion of data to a second location in the buffer; and
send, upon completion of the storing of the second portion of data, a second write pointer identifying the second location to indicate the second portion of the data is ready to be consumed;
a companion router comprising routing circuitry configured to merge respective at least the first write pointer and the second write pointer sent from respective ones of the plurality of producer DMA engines into a single updated write pointer; and
a consumer DMA engine comprising circuitry configured to consume the respective first portion of data and the second portion of data from the buffer according to the single updated write pointer.
2 . The apparatus of claim 1 , wherein the plurality of producer DMA engines individually comprise additional circuitry configured to advance a current location of a read pointer by a programmable skip amount of one or more data credits to generate a respective location in the buffer.
3 . The apparatus of claim 1 , wherein the first portion of data and the second portion of data are portions of a superframe of a video sequence and the buffer is a circular buffer with a size that is smaller than a size of the superframe.
4 . The apparatus of claim 3 , the routing circuitry further configured to:
manage initialization and updating of routing tables in a plurality of routers; and
retrieve route descriptors for the superframe from a corresponding route descriptor queue and initialize route entries in the plurality of routers.
5 . The apparatus of claim 1 , wherein:
the consumer DMA engine is one of a plurality of consumer DMA engines respectively comprising circuitry configured to:
consume a respective portion of data from a respective location in the buffer; and
send, upon completion of the consuming, a read pointer identifying the respective location to indicate the respective portion of the data has been consumed;
the routing circuitry is further configured to merge respective read pointers sent from respective ones of the plurality of consumer DMA engines into a single updated read pointer; and
the plurality of producer DMA engines individually comprise additional circuitry configured to store additional portions of data according to the single updated read pointer.
6 . The apparatus of claim 5 , wherein the plurality of consumer DMA engines individually comprise additional circuitry configured to advance a current location of the single updated write pointer by a programmable skip amount of one or more data credits to generate the respective location in the buffer.
7 . The apparatus of claim 5 , wherein the plurality of producer DMA engines individually comprise additional circuitry configured to determine whether space is available to receive the respective portion of data at the respective location in the buffer, and responsive to determining that space is not available, wait for an update of the single updated read pointer prior to storing the respective portion of data to a respective location in the buffer.
8 . A method, comprising:
performing, by circuitry of first producer direct memory access (DMA) engine:
storing a first portion of data to a first location in a buffer, the buffer comprising data received from the plurality of producer DMA engines including the first DMA engine and a second DMA engine; and
sending, upon completion of the storing of the first portion, a first write pointer identifying the first location to indicate the first portion of the data is ready to be consumed;
performing, by circuitry of a second producer direct memory access (DMA) engine:
storing a second portion of data to a second location in a buffer; and
sending, upon completion of the storing of the second portion, a second write pointer identifying the second location to indicate the second portion of the data is ready to be consumed;
merging, by routing circuitry, at least the first write pointer and the second write pointer into a single updated write pointer; and
consuming, by circuitry of a consumer DMA engine, the first portion of data and the second portion of data from the buffer according to the single updated write pointer.
9 . The method of claim 8 , further comprising advancing, by additional circuitry of individual engines of the plurality of producer DMA engines, a current location of a read pointer by a programmable skip amount of one or more data credits to generate a respective location in the buffer.
10 . The method of claim 8 , wherein the first portion of data and the second portion of data are portions of a superframe of a video sequence and the buffer is a circular buffer with a size that is smaller than a size of the superframe.
11 . The method of claim 10 , further comprising performing, by the routing circuitry:
managing initialization and updating of routing tables in a plurality of routers; and
retrieving route descriptors for the superframe from a corresponding route descriptor queue and initialize route entries in the plurality of routers.
12 . The method of claim 8 , further comprising:
performing, by circuitry of a plurality of consumer DMA engines including the consumer DMA engine:
consuming a respective portion of data from a respective location in the buffer; and
sending, upon completion of the consuming, a read pointer identifying the respective location to indicate the respective portion of the data has been consumed;
merging, by the routing circuitry, respective read pointers sent from respective ones of the plurality of consumer DMA engines into a single updated read pointer; and
storing, by additional circuitry of individual engines of the plurality of producer DMA engines, additional portions of data according to the single updated read pointer.
13 . The method of claim 12 , further comprising advancing, by additional circuitry of individual engines of the plurality of consumer DMA engines, a current location of the single updated write pointer by respective programmable skip amounts of one or more data credits to generate the respective locations in the buffer.
14 . The method of claim 12 , further comprising determining, by additional circuitry of individual ones of the plurality of producer DMA engines, whether respective space is available to receive the respective portion of data at the respective location in the buffer, and responsive to determining that space is not available, wait for an update of the single updated read pointer prior to storing the respective portion of data to a respective location in the buffer.
15 . A system, comprising:
one or more processors;
a memory implementing a buffer to provide data to a plurality of consumer direct memory access (DMA) engines comprising a first consumer DMA engine and second consumer DMA engine;
the first consumer DMA engine comprising circuitry configured to:
consume a first portion of data from a first location in the buffer; and
send, upon completion of the consuming of the first portion of data, a first read pointer identifying the first location to indicate the first portion of the data has been consumed;
the second consumer DMA engine comprising circuitry configured to:
consume a second portion of data from a second location in the buffer; and
send, upon completion of the consuming of the second portion of data, a second read pointer identifying the second location to indicate the second portion of the data has been consumed;
routing circuitry configured to merge at least the first read pointer and the second read pointers sent into a single updated read pointer;
and a producer DMA engine comprising circuitry configured to store the respective an additional portion of data in the buffer according to the single updated read pointer.
16 . The system of claim 15 , wherein the plurality of consumer DMA engines individually comprise additional circuitry configured to advance a current location of a write pointer by a programmable skip amount of one or more data credits to generate a respective location in the buffer.
17 . The system of claim 15 , wherein the first portion of data and the second portion of data are portions of a superframe of a video sequence and the buffer is a circular buffer with a size that is smaller than a size of the superframe.
18 . The system of claim 17 , routing circuitry further configured to:
manage initialization and updating of routing tables in a plurality of routers; and
retrieve route descriptors for the superframe from a corresponding route descriptor queue and initialize route entries in the plurality of routers.
19 . The system of claim 15 , wherein:
the producer DMA engine is one of a plurality of producer DMA engines individually comprising circuitry configured to:
store a respective portion of data from a respective location in the buffer; and
send, upon completion of the storing, a write pointer identifying the respective location to indicate the respective portion of the data is ready to be consumed;
the routing circuitry is further configured to merge respective write pointers sent from respective ones of the plurality of producer DMA engines into a single updated write pointer; and
the plurality of consumer DMA engines individually comprise additional circuitry configured to consume the respective portions of data according to the single updated write pointer.
20 . The system of claim 19 , wherein the plurality of producer DMA engines individually comprise additional circuitry configured to advance a current location of the single updated read pointer by a programmable skip amount of one or more data credits to generate the respective location in the buffer.