Methods and circuitry for implementing first-in first-out structure
Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
1. A first-in first-out (FIFO) pointer circuit comprising:
a serial chain of N registers coupled in circle and configured to shift a pointer signal in response to a pointer clock; and
a pointer abnormality detector having a logic circuit with N inputs respectively coupled to N outputs of the N registers,
wherein, the logic circuit is configured to detect lack of the pointer signal or presence of multiple pointer signals.
2. The FIFO pointer circuit of claim 1 wherein the logic circuit in the pointer abnormality detector comprises:
a first logic gate having N−1 inputs, coupled to N−1 outputs of the N registers, and an output; and
a second logic gate having a first input coupled to the output of the first logic gate and a second input coupled to one output of the N registers that is not coupled to the first logic gate.
3. The FIFO pointer circuit of claim 2 wherein the logic circuit further comprises a first flip-flop having a data input coupled to an output of the second logic gate, a clock input and an output.
4. The FIFO pointer circuit of claim 2 wherein the first logic gate is an OR gate, and the second logic gate is an exclusive NOR gate.
5. The FIFO pointer circuit of claim 2 wherein the logic circuit further comprises:
a first flip-flop having a data input coupled to an output of the second logic gate, a clock input and an output;
a third logic gate having a first input coupled to a clock signal and a second input coupled to one output of the N registers that is not coupled to the first logic gate;
a second flip-flop having a data input coupled to an output of the second logic gate, a clock input coupled to an output of the third logic gate and an output; and
a fourth logic gate having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop and an output for generating a signal indicative of the lack of the pointer signal or the presence of multiple pointer signals.
6. The FIFO pointer circuit of claim 3 wherein the logic circuit in the pointer abnormality detector further comprises a third logic gate having a first input coupled to a clock signal and a second input coupled to one output of the N registers that is not coupled to the first logic gate.
7. The FIFO pointer circuit of claim 6 wherein the third logic gate is an AND gate.
8. The FIFO pointer circuit of claim 6 wherein the logic circuit further comprises a second flip-flop having a data input coupled to an output of the second logic gate, a clock input coupled to an output of the third logic gate and an output.
9. The FIFO pointer circuit of claim 8 wherein the logic circuit further comprises a fourth logic gate having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop and an output for generating a signal indicative of the lack of the pointer signal or the presence of multiple pointer signals.
10. The FIFO pointer circuit of claim 9 wherein the fourth logic gate is an OR gate.
11. A method of detecting an abnormality in a plurality of pointer signals comprising:
generating a first signal indicative of a lack of a pointer signal;
generating a second signal indicative of a presence of multiple pointer signals; and
combining the first and second signals to generate a pointer abnormality signal.
12. The method of claim 11 further comprising receiving a plurality of pointer signals from a serial chain of N registers coupled in circle and configured to shift a pointer signal in response to a pointer clock.
13. The method of claim 12 further comprising logically combining N outputs of the N registers to generate the first signal.
14. The method of claim 12 further comprising:
logically combining N−1 outputs of N−1 of the N registers; and
processing the combined N−1 outputs and one output of the N registers that is not one of the N−1 outputs to generate the second signal.
15. The method of claim 12 further comprising:
providing N−1 outputs of the N registers to a first logic gate having N−1 inputs; and
providing an output of the first logic gate to a first input of a second logic gate and a second input coupled to one output of the N registers that is not coupled to the first logic gate.
16. The method of claim 15 further comprising providing an output of the second logic gate to a data input of a first flip-flop.
17. The method of claim 16 further comprising providing a second input coupled to one output of the N registers that is not coupled to the first logic gate to first input of a third logic gate having a second input coupled to a clock signal.
18. The method of claim 17 further comprising providing an output of the second logic gate to a data input of a second flip-flop having a clock input coupled to an output of the third logic gate.
19. The method of claim 18 further comprising providing outputs of the first flip-flop and the second flip-flop to a fourth logic gate.
20. The method of claim 19 further comprising generating, by the fourth logic gate, a signal indicative of the lack of the pointer signal or the presence of multiple pointer signals.