Synchronized solid-state imaging element, imaging device, and electronic device
There is provided a solid-state imaging element in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.
1. A light detecting device comprising:
a pixel circuit including a pixel array unit configured to output a pixel signal; and
a plurality of separate signal processing circuits configured to receive the pixel signal, each separate signal processing circuit including a separate and distinct row decoder and a separate and distinct column decoder,
wherein the plurality of separate signal processing circuits are physically separated from each other,
wherein a common reference clock is configured to supply to the plurality of separate signal processing circuits, and
wherein the pixel circuit overlaps the plurality of separate signal processing circuits.
2. The light detecting device according to claim 1 , further comprising
a multiplier unit configured to multiply a reference clock supplied to the plurality of separate signal processing circuits,
wherein the plurality of separate signal processing circuits use a clock signal multiplied by the reference clock by the multiplier unit for signal processing.
3. The light detecting device according to claim 2 ,
wherein the multiplier unit is included in one signal processing circuit of the plurality of separate signal processing circuits, and
a reference clock is supplied to the one signal processing circuit of the plurality of separate signal processing circuits, and a clock signal multiplied by the multiplier unit is supplied to a signal processing circuit other than the one signal processing circuit of the plurality of separate signal processing circuits.
4. The light detecting device according to claim 3 ,
wherein the reference clock and the clock signal multiplied by the reference clock are supplied to the plurality of separate signal processing circuits.
5. The light detecting device according to claim 1 ,
wherein a reference clock is supplied to one of the plurality of separate signal processing circuits and a signal processing circuit to which the reference clock is supplied supplies the reference clock to another signal processing circuit.
6. The light detecting device according to claim 1 , further comprising
a multiplier unit configured to multiply a reference clock supplied to the plurality of separate signal processing circuits,
wherein at least one of the plurality of separate signal processing circuits includes
an analog signal processing unit configured to perform analog signal processing on a clock signal multiplied by the reference clock by the multiplier unit, and
a digital signal processing unit configured to perform digital signal processing on a clock signal multiplied by the multiplier unit in another signal processing circuit to which the reference clock is supplied.
7. An imaging device comprising:
a pixel circuit including a pixel array unit configured to output a pixel signal; and
a plurality of separate signal processing circuits configured to receive the pixel signal, each separate signal processing circuit including a separate and distinct row decoder and a separate and distinct column decoder,
wherein the plurality of separate signal processing circuits are physically separated from each other,
wherein a common reference clock is configured to supply to the plurality of separate signal processing circuits, and
wherein the pixel circuit overlaps the plurality of separate signal processing circuits.
8. The imaging device according to claim 7 , further comprising
a multiplier unit configured to multiply a reference clock supplied to the plurality of separate signal processing circuits,
wherein the plurality of separate signal processing circuits use a clock signal multiplied by the reference clock by the multiplier unit for signal processing.
9. The imaging device according to claim 8 ,
wherein the multiplier unit is included in one signal processing circuit of the plurality of separate signal processing circuits, and
a reference clock is supplied to the one signal processing circuit of the plurality of separate signal processing circuits, and a clock signal multiplied by the multiplier unit is supplied to a signal processing circuit other than the one signal processing circuit of the plurality of separate signal processing circuits.
10. The imaging device according to claim 9 ,
wherein the reference clock and the clock signal multiplied by the reference clock are supplied to the plurality of separate signal processing circuits.
11. The imaging device according to claim 7 ,
wherein a reference clock is supplied to one of the plurality of separate signal processing circuits and a signal processing circuit to which the reference clock is supplied supplies the reference clock to another signal processing circuit.
12. The imaging device according to claim 7 , further comprising
a multiplier unit configured to multiply a reference clock supplied to the plurality of separate signal processing circuits,
wherein at least one of the plurality of separate signal processing circuits includes
an analog signal processing unit configured to perform analog signal processing on a clock signal multiplied by the reference clock by the multiplier unit, and
a digital signal processing unit configured to perform digital signal processing on a clock signal multiplied by the multiplier unit in another signal processing circuit to which the reference clock is supplied.
13. An electronic device comprising:
a pixel circuit including a pixel array unit configured to output a pixel signal; and
a plurality of separate signal processing circuits configured to receive the pixel signal, each separate signal processing circuit including a separate and distinct row decoder and a separate and distinct column decoder,
wherein the plurality of separate signal processing circuits are physically separated from each other,
wherein a common reference clock is configured to supply to the plurality of separate signal processing circuits, and
wherein the pixel circuit overlaps the plurality of separate signal processing circuits.
14. The electronic device according to claim 13 , further comprising
a multiplier unit configured to multiply a reference clock supplied to the plurality of separate signal processing circuits,
wherein the plurality of separate signal processing circuits use a clock signal multiplied by the reference clock by the multiplier unit for signal processing.
15. The electronic device according to claim 14 ,
wherein the multiplier unit is included in one signal processing circuit of the plurality of separate signal processing circuits, and
a reference clock is supplied to the one signal processing circuit of the plurality of separate signal processing circuits, and a clock signal multiplied by the multiplier unit is supplied to a signal processing circuit other than the one signal processing circuit of the plurality of separate signal processing circuits.
16. The electronic device according to claim 15 ,
wherein the reference clock and the clock signal multiplied by the reference clock are supplied to the plurality of separate signal processing circuits.
17. The electronic device according to claim 13 ,
wherein a reference clock is supplied to one of the plurality of separate signal processing circuits and a signal processing circuit to which the reference clock is supplied supplies the reference clock to another signal processing circuit.
18. The electronic device according to claim 13 , further comprising
a multiplier unit configured to multiply a reference clock supplied to the plurality of separate signal processing circuits,
wherein at least one of the plurality of separate signal processing circuits includes
an analog signal processing unit configured to perform analog signal processing on a clock signal multiplied by the reference clock by the multiplier unit, and
a digital signal processing unit configured to perform digital signal processing on a clock signal multiplied by the multiplier unit in another signal processing circuit to which the reference clock is supplied.