Memory with FRAM and SRAM of IC
Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. The first memory array and the second memory array share the same bus. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, and a ferroelectric layer over the gate electrode.
1. A memory, comprising:
a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array; and
a plurality of static random access memory (SRAM) cells arranged in a second memory array,
wherein the first memory array and the second memory array share the same bus,
wherein each of the FRAM cells comprises a ferroelectric field-effect transistor (FeFET), and a gate structure of the FeFET comprises:
a gate electrode over a channel of the FeFET;
a ferroelectric layer over the gate electrode;
a first electrode over the gate electrode; and
a second electrode over the first electrode,
wherein the ferroelectric layer is formed between the first and second electrodes.
2. The memory as claimed in claim 1 , wherein size of each of the SRAM cells is greater than that of each of the FRAM cell.
3. The memory as claimed in claim 1 , wherein the number of transistors of each of the SRAM cells is greater than that of each of the FRAM cells.
4. The memory as claimed in claim 1 , wherein material of the ferroelectric layer comprises HfO2, HfSiOx, HfZrOx, Al2O3, TiO2, LaOx, BaSrTiOx (BST) or PbZrTiOx (PZT).
5. The memory as claimed in claim 1 , wherein number of the FRAM cells in the first memory array is greater than that of the SRAM cells in the second memory array.
6. The memory as claimed in claim 1 , wherein the gate structure of the FeFET further comprises:
an interfacial layer formed between the channel of the FeFET and the gate electrode.
7. The memory as claimed in claim 6 , wherein the gate structure of the FeFET further comprises:
a dielectric layer of high-K material formed between the interfacial layer and the gate electrode.
8. The memory as claimed in claim 1 , wherein the gate structure of the FeFET further comprises:
a metal layer between the gate electrode and the ferroelectric layer.
9. An integrated circuit (IC), comprising:
a memory, comprising:
a first memory array formed by a plurality of ferroelectric random access memory (FRAM) cells;
a second memory array formed by a plurality of static random access memory (SRAM) cells; and
a first bus coupled to and shared by the first and second memory arrays;
a second bus coupled to the first bus; and
a controller coupled to the memory through the first bus and the second bus, and configured to access the first memory array with a first access rate when an obtained access rate is less than or equal to a predetermined rate and the second memory array with a second access rate when the obtained access rate is greater than the predetermined rate through the first bus and the second bus,
wherein the first access rate is slower than the second access rate.
10. The IC as claimed in claim 9 , wherein the number of the FRAM cells is greater than that of the SRAM cells, and size of the SRAM cell is greater than that of the FRAM cell.
11. The IC as claimed in claim 9 , wherein number of transistors of the SRAM cell is greater than that of the FRAM cell.
12. The IC as claimed in claim 9 , wherein the SRAM cell comprises two P-type transistors and four N-type transistors, and the N-type and P-type transistors are fin field effect transistors (FinFETs).
13. The IC as claimed in claim 9 , wherein the FRAM cell comprises a transistor and a ferroelectric capacitor, and the transistor is a FinFET.
14. The IC as claimed in claim 9 , wherein the FRAM cell comprises a ferroelectric field-effect transistor (FeFET).
15. A memory, comprising:
a first memory array comprising a plurality of ferroelectric random access memory (FRAM) cells;
a second memory array comprising a plurality of static random access memory (SRAM) cells; and
a bus coupled to the first and second memory arrays,
wherein the first memory array is accessed through the bus when an access rate is less than or equal to a predetermined rate, and the second memory array is accessed through the bus when the access rate is greater than the predetermined rate,
wherein each of the FRAM cells comprises a ferroelectric field-effect transistor (FeFET), and a gate structure of the FeFET comprises:
a gate electrode over a channel of the FeFET;
a ferroelectric layer over the gate electrode;
a first electrode over the gate electrode; and
a second electrode over the first electrode,
wherein the ferroelectric layer is formed between the first and second electrodes.
16. The memory as claimed in claim 15 , wherein a gate structure of the FeFET comprises:
an interfacial layer between the channel of the FeFET and the gate electrode.
17. The memory as claimed in claim 16 , wherein a gate structure of the FeFET comprises:
a dielectric layer of high-K material between the interfacial layer and the gate electrode.
18. The memory as claimed in claim 1 , wherein the first memory array and the second memory array are accessed with different rates through the same bus.
19. The memory as claimed in claim 15 , wherein the gate structure of the FeFET further comprises:
a metal layer between the gate electrode and the ferroelectric layer.
20. The memory as claimed in claim 15 , wherein size of each of the SRAM cells is greater than that of each of the FRAM cell.