Reduced source/drain coupling for CFET
A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.
1. A complementary field effect transistor (CFET) device comprising:
an nFET channel device and a pFET channel device; and
an airgap defined directly between the nFET channel device and the pFET channel device such that a width of the airgap is approximately equal to a width of the nFET channel device.
2. The CFET of claim 1 , wherein the airgap is horizontally aligned with a dielectric layer.
3. The CFET of claim 2 , wherein the airgap is vertically aligned with at least one metal contact.
4. The CFET of claim 3 , wherein the nFET channel device and the pFET channel device are disposed between a plurality of nanosheet stacks.
5. The CFET of claim 4 , wherein each of the plurality of nanosheet stacks includes alternating layers of a first material and a second material.
6. The CFET of claim 1 , wherein a size of the pFET channel device is greater than a size of the nFET channel device.
7. The CFET of claim 1 , wherein a dielectric defines sidewall boundaries of the airgap.
8. The CFET of claim 7 , wherein the dielectric directly contacts portions of a top surface of the pFET channel device.
9. The CFET of claim 7 , wherein the dielectric directly contacts portions of a bottom surface of the nFET channel device.
10. The CFET of claim 1 , wherein an upper boundary and a lower boundary of the airgap are defined by a bottom surface of the nFET channel device and a top surface of the pFET channel device, respectively.
11. A complementary field effect transistor (CFET) device comprising:
an nFET channel device;
a pFET channel device vertically aligned with the nFET channel device; and
an airgap defined directly between the nFET channel device and the pFET channel device.
12. The CFET of claim 11 , wherein the airgap is horizontally aligned with a dielectric layer.
13. The CFET of claim 12 , wherein the airgap is vertically aligned with at least one metal contact.
14. The CFET of claim 13 , wherein the nFET channel device and the pFET channel device are disposed between a plurality of nanosheet stacks.
15. The CFET of claim 14 , wherein each of the plurality of nanosheet stacks includes alternating layers of a first material and a second material.
16. The CFET of claim 11 , wherein a size of the pFET channel device is greater than a size of the nFET channel device.
17. The CFET of claim 11 , wherein a width of the airgap is approximately equal to a width of the nFET channel device.
18. The CFET of claim 11 , wherein a dielectric defines sidewall boundaries of the airgap.
19. The CFET of claim 11 , wherein an upper boundary and a lower boundary of the airgap are defined by a bottom surface of the nFET channel device and a top surface of the pFET channel device, respectively.