Reduced source/drain coupling for CFET
A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.
1. A method for reducing capacitance coupling, the method comprising:
forming a nanosheet stack including alternating layers of a first material and a second material over a substrate;
forming a source/drain epi for a first device;
depositing a sacrificial material over the source/drain epi;
forming a source/drain epi for a second device over the sacrificial material; and
removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.
2. The method of claim 1 , wherein a dielectric is directionally deposited over the source/drain epi for the second device.
3. The method of claim 2 , wherein an inter-layer-dielectric (ILD) is deposited over the dielectric.
4. The method of claim 3 , wherein the alternating layers of the first material are removed to form openings.
5. The method of claim 4 , wherein a high-k metal gate (HKMG) is deposited in the openings formed from the removal of the alternating layers of the first material.
6. The method of claim 5 , wherein a sacrificial cap is deposited over the HKMG.
7. A method for reducing capacitance coupling, the method comprising:
forming a nanosheet stack including alternating layers of a first material and a second material over a substrate;
forming a dummy gate over the nanosheet stack;
selectively etching one layer of the alternating layers to define a gap within the nanosheet stack;
filling the gap with a first spacer material;
recessing the nanosheet stack and etching the first material of the alternating layers to create a plurality of nanosheet stacks and indentations within each of the plurality of nanosheet stacks;
filling the indentations with a second spacer material;
forming a source/drain epi for a first device between the plurality of nanosheet stacks;
depositing a sacrificial material over the source/drain epi;
forming a source/drain epi for a second device over the sacrificial material; and
removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.
8. The method of claim 7 , wherein a dielectric is directionally deposited over the source/drain epi for the second device.
9. The method of claim 8 , wherein an inter-layer-dielectric (ILD) is deposited over the dielectric.
10. The method of claim 9 , wherein the alternating layers of the first material are removed to form openings.
11. The method of claim 10 , wherein a high-k metal gate (HKMG) is deposited in the openings formed from the removal of the alternating layers of the first material.
12. The method of claim 11 , wherein a sacrificial cap is deposited over the HKMG.
13. The method of claim 12 , wherein contacts are formed to the source/drain epi for the first device and the source/drain epi for the second device.
14. The method of claim 13 , wherein the airgap is vertically aligned with at least one of the contacts.
15. The method of claim 14 , wherein the airgap is horizontally aligned with the first spacer material.