Semiconductor device
A semiconductor device includes a substrate, an active pattern on the substrate, a plurality of lower nanosheets stacked on the active pattern, a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including first to third layers sequentially stacked on each other, a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked on the separation structure, and a gate electrode extending in a second horizontal direction different from the first horizontal direction, and surrounding the separation structure, each of the plurality of lower nanosheets, and each of the plurality of upper nanosheets. The first and third layers include the same material, and each of the first layer and the third layer includes a material different from a material of the second layer.
1 . A semiconductor device comprising:
a substrate;
an active pattern extending in a first horizontal direction on the substrate;
a plurality of lower nanosheets stacked, while being spaced apart from each other in a vertical direction, on the active pattern;
a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including a first layer, a second layer, and a third layer sequentially stacked on each other;
a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked, while being spaced apart from each other in the vertical direction, on the separation structure; and
a gate electrode extending in a second horizontal direction different from the first horizontal direction, and surrounding the separation structure, each lower nanosheet of the plurality of lower nanosheets, and each upper nanosheet of the plurality of upper nanosheets to form a multi-bridge channel field effect transistor,
wherein the first layer and the third layer include the same material, and
wherein each of the first layer and the third layer includes a material different from a material of the second layer.
2 . The semiconductor device of claim 1 ,
wherein the second layer includes the same material as each lower nanosheet of the plurality of lower nanosheets and each upper nanosheet of the plurality of upper nanosheets.
3 . The semiconductor device of claim 1 ,
wherein a thickness of the second layer in the vertical direction is smaller than each of a thickness of the first layer in the vertical direction and a thickness of the third layer in the vertical direction.
4 . The semiconductor device of claim 1 ,
wherein a thickness of the second layer in the vertical direction is smaller than each of a thickness of each lower nanosheet of the plurality of lower nanosheets in the vertical direction and a thickness of each upper nanosheet of the plurality of upper nanosheets in the vertical direction.
5 . The semiconductor device of claim 1 , further comprising:
an interlayer insulating layer contacting sidewalls of the separation structure in the first horizontal direction.
6 . The semiconductor device of claim 1 , further comprising:
a lower source/drain region disposed on sidewalls of the plurality of lower nanosheets; and
an upper source/drain region disposed on sidewalls of the plurality of upper nanosheets,
wherein the upper source/drain region is spaced apart from the lower source/drain region in the vertical direction, and
wherein each of the lower source/drain region and the upper source/drain region does not contact the separation structure.
7 . The semiconductor device of claim 1 , further comprising:
a gate insulating layer disposed between the gate electrode and the separation structure, and contacting an uppermost surface of the separation structure.
8 . The semiconductor device of claim 1 , further comprising:
a gate insulating layer disposed between the gate electrode and the separation structure; and
an interface layer disposed between the gate insulating layer and an uppermost surface of the separation structure, and contacting the uppermost surface of the separation structure.
9 . The semiconductor device of claim 8 ,
wherein the interface layer is disposed between the first layer and the second layer, and between the second layer and the third layer.
10 . The semiconductor device of claim 1 , further comprising:
a gate insulating layer disposed between the gate electrode and sidewalls of the second layer; and
an interface layer disposed between the gate insulating layer and the sidewalls of the second layer, and contacting the sidewalls of the second layer.
11 . The semiconductor device of claim 1 , further comprising:
a gate insulating layer disposed between the gate electrode and the plurality of lower nanosheets; and
an interface layer disposed between the gate insulating layer and each lower nanosheet of the plurality of lower nanosheets,
wherein the second layer includes the same material as the interface layer.
12 . The semiconductor device of claim 1 ,
wherein the gate electrode further includes:
a first gate electrode surrounding each lower nanosheet of the plurality of lower nanosheets, and
a second gate electrode surrounding each upper nanosheet of the plurality of upper nanosheets, and
wherein the second gate electrode is spaced apart from the first gate electrode in the vertical direction.
13 . The semiconductor device of claim 1 ,
wherein the gate electrode includes a first portion surrounding the separation structure, a second portion surrounding each lower nanosheet of the plurality of lower nanosheets, and a third portion surrounding each upper nanosheet of the plurality of upper nanosheets, and
wherein the first portion is connected to the second portion and the third portion.