Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device includes a first fin structure. The semiconductor device structure also includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction.
1. A semiconductor device structure, comprising:
a first device formed over a substrate, wherein the first device comprises a first fin structure, wherein the first fin structure has a first height;
a second device formed over or below the first device, wherein the second device comprises a plurality of second nanostructures stacked in a vertical direction, and each of the second nanostructures has a second height, and the first height is greater than the second height; and
a first inner gate spacer and in direct contact with the first fin structure, wherein a topmost surface of the first inner gate spacer is in direct contact with a bottommost surface of the first fin structure.
2. The semiconductor device structure as claimed in claim 1 , wherein one of the first device and the second device is a P-type device and the other is an N-type device.
3. The semiconductor device structure as claimed in claim 1 , further comprising:
a first gate stack wrapped around the first fin structure; and
a second gate stack wrapped around the second nanostructures.
4. The semiconductor device structure as claimed in claim 3 , further comprising:
a second inner gate spacer between the first gate stack and the second gate stack.
5. The semiconductor device structure as claimed in claim 3 , wherein the first gate stack comprises a first portion and a second portion, the first portion is next to a sidewall of the second gate stack, and the second portion is directly below the second gate stack.
6. The semiconductor device structure as claimed in claim 1 , further comprising:
an isolation structure formed over the substrate; and
the first inner gate spacer extended above the substrate, wherein a bottom surface of the first inner gate spacer is lower than a top surface of the isolation structure.
7. The semiconductor device structure as claimed in claim 1 , further comprising:
a sidewall spacer between two adjacent second nanostructures;
a second S/D structure formed on a sidewall of one of the second nanostructures; and
a second gate stack wrapped around the second nanostructures, wherein the sidewall spacer is between the second gate stack and the second S/D structure.
8. The semiconductor device structure as claimed in claim 7 , further comprising:
a first S/D structure formed on a sidewall of the first fin structure; and
an etch stop layer between the first S/D structure and the second S/D structure.
9. The semiconductor device structure as claimed in claim 1 , wherein one of the first device and the second device is a logic circuit device, and the other is a static random access memory (SRAM).
10. A semiconductor device structure, comprising:
a first device formed over a substrate, wherein the first device comprises a first fin structure, the first fin structure has a first height;
a first gate stack wrapped around the first fin structure;
a second device formed over the first device, wherein the second device comprises a plurality of second nanostructures stacked in a vertical direction, each of the second nanostructures has a second height, and the first height is greater than the second height;
a second gate stack wrapped around the second nanostructures; and
a first inner gate spacer formed between a sidewall of the first gate stack and a sidewall of the second gate stack, wherein a top surface of the first gate stack, a top surface of the first inner gate spacer and a top surface of the second gate stack are at a same level.
11. The semiconductor device structure as claimed in claim 10 , further comprising:
a sidewall spacer formed between two adjacent second nanostructures; and
an S/D structure formed on a sidewall of one of the second nanostructures,
wherein the sidewall spacer is between the second gate stack and the S/D structure.
12. The semiconductor device structure as claimed in claim 10 , further comprising:
an etch stop layer between the first gate stack and the second gate stack.
13. The semiconductor device structure as claimed in claim 10 , wherein one of the first device and the second device is a logic circuit device, and the other is a static random access memory (SRAM).
14. The semiconductor device structure as claimed in claim 10 , wherein one of the first device and the second device is a P-type device and the other is an N-type device.
15. The method for forming the semiconductor device structure as claimed in claim 10 , further comprising:
a second inner gate spacer below the second gate stack, wherein the second inner gate spacer comprises a top surface in direct contact with the second gate stack and a bottom surface in direct contact with the first gate stack.
16. A semiconductor device structure, comprising:
a plurality of first nanostructures formed over a substrate, wherein the first nanostructures are stacked in a vertical direction;
a first gate stack wrapped around the first nanostructures;
a first inner gate spacer formed over the first nanostructures;
a second fin structure formed over the first inner gate spacer; and
a second gate stack wrapped around the second fin structure, wherein a first sidewall of the first inner gate spacer is aligned with a first sidewall of the second fin structure, and a second sidewall of the first inner gate spacer is aligned with a second sidewall of the second fin structure,
wherein the first gate stack is different and separated from the second gate stack, and wherein the first inner gate spacer is between the first gate stack and the second gate stack.
17. The semiconductor device structure as claimed in claim 16 , wherein the second fin structure is in direct contact with the first inner gate spacer.
18. The semiconductor device structure as claimed in claim 16 , wherein the first gate stack comprises a first portion and a second portion, the first portion is next to a sidewall of the second gate stack, and the second portion is directly below the second gate stack.
19. The semiconductor device structure as claimed in claim 18 , further comprising:
a second inner gate spacer between the first portion of the first gate stack and the second gate stack.
20. The semiconductor device structure as claimed in claim 16 , wherein the first gate stack has a first thickness, the second gate stack has a second thickness, and the second thickness is smaller than the first thickness.