Stacked field-effect transistors
Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top active region. The width of the top of the top active region is smaller than the width of bottom of the top active region. The stacked FET further comprises a top contact in direct contact with a top surface of the top active region. The stacked FET further comprises a bottom active region located substantially below the top active region. The stacked FET further comprises a bottom contact in direct contact with a top surface of the bottom active region. The bottom contact is wider at a top end than at a bottom end.
1 . A stacked field-effect transistor (FET) comprising:
a top active region, wherein the width of the top of the top active region is smaller than the width of the bottom of the top active region;
a top contact in direct contact with a top surface of the top active region;
a bottom active region located substantially below the top active region; and
a bottom contact in direct contact with a top surface of the bottom active region, the bottom contact being wider at a top end than at a bottom end such that a horizontal distance between the bottom contact and the top active region is substantially identical from a bottom surface of the top active region to the top surface of the top active region.
2 . The stacked FET of claim 1 , wherein the bottom contact extends vertically from the top surface of the bottom active region and lateral to the top active region.
3 . The stacked FET of claim 1 , wherein the top and bottom active regions are nanosheet transistor regions having the same doping type.
4 . The stacked FET of claim 1 , wherein the top and bottom active regions are nanosheet transistor regions having different doping types.
5 . The stacked FET of claim 1 , wherein the top active region has a substantially trapezoidal shape.
6 . A stacked field-effect transistor (FET) comprising:
a top device comprising a top epi region that is stacked over a bottom device that comprises a bottom epi region;
a trapezoidal bottom contact in direct contact with the bottom epi region, the trapezoidal bottom contact comprising a sloped sidewall resulting from being wider at a top end than at a bottom end; and
a dielectric liner in direct contact with the sloped sidewall of the trapezoidal bottom contact and in direct contact with an entirety of a side surface of the top epi region, wherein the sloped sidewall of the trapezoidal bottom contact is substantially parallel with the side surface of the top epi region.
7 . The stacked FET of claim 6 , further comprising:
an elongated airgap enclosed within the dielectric liner.
8 . The stacked FET of claim 6 , further comprising:
a middle isolation layer in direct contact with the bottom epi region, in direct contact with the top epi region, and in direct contact with the dielectric liner.
9 . The stacked FET of claim 8 , wherein the middle isolation layer is further in direct contact with the trapezoidal bottom contact.