Devices including stacked nanosheet transistors

1. A nanosheet transistor device comprising:

a lower nanosheet transistor having a first nanosheet width;

an upper tri-gate nanosheet transistor on an upper surface of the lower nanosheet transistor and having a second nanosheet width that is narrower than the first nanosheet width; and

an insulation region that comprises oxygen and is on the upper surface of the lower nanosheet transistor and a sidewall of the upper tri-gate nanosheet transistor.

2. The nanosheet transistor device of claim 1 ,

wherein the lower nanosheet transistor comprises a lower gate that is wider than an upper gate of the upper tri-gate nanosheet transistor,

wherein the sidewall of the upper tri-gate nanosheet transistor comprises a sidewall of the upper gate, and

wherein the insulation region contacts the sidewall of the upper gate.

3. The nanosheet transistor device of claim 1 ,

wherein the lower nanosheet transistor further comprises a plurality of lower nanosheets,

wherein the upper tri-gate nanosheet transistor further comprises a plurality of upper nanosheets that overlap the plurality of lower nanosheets, and

wherein the insulation region contacts at least one of the plurality of upper nanosheets.

4. The nanosheet transistor device of claim 1 ,

wherein the lower nanosheet transistor is a tri-gate nanosheet transistor or a gate-all-around (GAA) nanosheet transistor,

wherein the upper tri-gate nanosheet transistor comprises a gate insulation layer, and

wherein the insulation region contacts the gate insulation layer.

5. The nanosheet transistor device of claim 1 , wherein the insulation region comprises a multi-layer spacer comprising:

a first layer comprising the oxygen; and

a second layer that is between the first layer and the sidewall of the upper tri-gate nanosheet transistor.

6. The nanosheet transistor device of claim 5 , wherein the second layer is a blocking layer that comprises nitride.

7. A nanosheet transistor device comprising:

a transistor stack comprising:

a lower nanosheet transistor comprising a plurality of lower nanosheets, the lower nanosheet transistor having a first nanosheet width and a lower gate width;

an upper nanosheet transistor comprising a plurality of upper nanosheets on the lower nanosheet transistor, the upper nanosheet transistor having a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively; and

an insulation region comprising a sidewall that contacts at least one of the plurality of lower nanosheets and is on a sidewall of a gate of the lower nanosheet transistor, or contacts at least one of the plurality of upper nanosheets and is on a sidewall of a gate of the upper nanosheet transistor,

wherein the lower nanosheet transistor or the upper nanosheet transistor further comprises a gate insulation layer comprising an end portion that is on the sidewall of the insulation region.

8. The nanosheet transistor device of claim 7 , wherein the insulation region is on the sidewall of the gate of the lower nanosheet transistor and is configured to modulate a threshold voltage of the lower nanosheet transistor.

9. The nanosheet transistor device of claim 7 , wherein the insulation region is on the sidewall of the gate of the upper nanosheet transistor and is configured to modulate a threshold voltage of the upper nanosheet transistor.

10. The nanosheet transistor device of claim 7 , wherein the insulation region comprises a spacer that comprises oxygen and has a lower dielectric constant than the gate insulation layer.

11. The nanosheet transistor device of claim 7 , wherein the lower nanosheet transistor and the upper nanosheet transistor are a gate-all-around (GAA) nanosheet transistor and a tri-gate nanosheet transistor, respectively, or vice versa, or are respective tri-gate nanosheet transistors.

12. The nanosheet transistor device of claim 7 , wherein the gate of the lower nanosheet transistor contacts the gate of the upper nanosheet transistor.

13. The nanosheet transistor device of claim 7 , further comprising an insulation layer that separates the gate of the lower nanosheet transistor from the gate of the upper nanosheet transistor.

14. The nanosheet transistor device of claim 7 ,

wherein the sidewall of the insulation region contacts the end portion of the gate insulation layer, and

wherein the gate insulation layer has a higher dielectric constant than the insulation region.

15. The nanosheet transistor device of claim 14 , wherein the end portion of the gate insulation layer comprises fluorine.

16. A nanosheet transistor device comprising:

a lower nanosheet transistor having a first nanosheet width;

an upper tri-gate nanosheet transistor on an upper surface of the lower nanosheet transistor and having a second nanosheet width that is narrower than the first nanosheet width; and

an insulation region that comprises oxygen and is on the upper surface of the lower nanosheet transistor and is in contact with a sidewall of the upper tri-gate nanosheet transistor.

17. The nanosheet transistor device of claim 16 ,

wherein the lower nanosheet transistor is a tri-gate nanosheet transistor or a gate-all-around (GAA) nanosheet transistor,

wherein the upper tri-gate nanosheet transistor comprises a gate insulation layer, and

wherein the insulation region is in contact with the gate insulation layer.

18. The nanosheet transistor device of claim 16 , wherein the insulation region comprises a multi-layer spacer comprising:

a first layer comprising the oxygen; and

a second layer that is between the first layer and the sidewall of the upper tri-gate nanosheet transistor.

19. The nanosheet transistor device of claim 18 , wherein the second layer is a blocking layer that comprises nitride.

20. The nanosheet transistor device of claim 16 , wherein the insulation region is configured to modulate a threshold voltage of the upper tri-gate nanosheet transistor.