Three-dimensional stacked semiconductor device including simplified source/drain contact area
Provided is a semiconductor device which includes: a 1 st source/drain pattern for a 1 st transistor; a 2 nd source/drain pattern for a 2 nd transistor, above the 1 st source/drain pattern, the 2 nd source/drain pattern having a smaller width than the 1 st source/drain pattern in a channel-width direction; a 1 st isolation layer surrounding the 1 st source/drain pattern; a 2 nd isolation layer surrounding the 2 nd source/drain pattern, the 1 st and 2 nd isolation layers including a first material; a liner surrounding the 1 st source/drain pattern, the liner including a 2 nd material; and a contact structure on the 1 st source/drain pattern, wherein the contact structure penetrates the 2 nd isolation layer and the liner to contact the 1 st source/drain pattern without penetrating the 1 st isolation layer.
1. A semiconductor device comprising:
a 1 st channel structure extended in a 1 st direction;
a 2 nd channel structure extended in the 1 st direction above the 1 st channel structure, the 2 nd channel structure having a smaller width than the 1 st channel structure in a 2 nd direction intersecting the 1 st direction;
a 1 st source/drain pattern on the 1 st channel structure;
a 2 nd source/drain pattern on the 2 nd channel structure, the 2 nd source/drain pattern having a smaller width than the 1 st source/drain pattern in the 2 nd direction;
a 1 st liner on the 1 st source/drain pattern; and
a 1 st isolation layer surrounding the 1 st source/drain pattern with the 1 st liner thereon,
wherein the 1 st liner comprises:
a 1 st portion surrounding an outer surface of the 1 st source/drain pattern; and
a liner portion protruded from the 1 st portion toward the 2 nd source/drain pattern in a 3 rd direction intersecting the 1 st direction and the 2 nd direction.
2. The semiconductor device of claim 1 , wherein the 1 st isolation layer and the 1 st liner comprise different materials.
3. The semiconductor device of claim 2 , wherein the 1 st isolation layer comprises an oxide material, and the 1 st liner comprises a nitride material.
4. The semiconductor device of claim 1 , wherein the liner portion has a greater width than the 2 nd source/drain pattern in the 2 nd direction.
5. The semiconductor device of claim 1 , wherein a part of the liner portion is above the 1 st source/drain pattern with a gap portion of the 1 st isolation layer therebetween in the 3 rd direction.
6. The semiconductor device of claim 5 , further comprising:
a 2 nd isolation layer surrounding the 2 nd source/drain pattern; and
a contact structure penetrating the 2 nd isolation layer, the part of the liner portion, the gap portion of the 1 st isolation layer, and the 1 st portion of the 1 st liner to contact the 1 st source/drain pattern.
7. The semiconductor device of claim 6 , further comprising a 2 nd liner on the 2 nd source/drain pattern and the 1 st portion of the 1 st liner,
wherein the contact structure penetrates the 2 nd liner to contact the 1 st source/drain pattern.
8. The semiconductor device of claim 1 , wherein the liner portion has a smaller width than the 1 st source/drain pattern in the 2 nd direction.
9. The semiconductor device of claim 8 , further comprising:
a 2 nd isolation layer surrounding the 2 nd source/drain pattern; and
a contact structure penetrating the 2 nd isolation layer and the 1 st portion of the 1 st liner to contact the 1 st source/drain pattern.
10. The semiconductor device of claim 9 , further comprising a 2 nd liner on the 2 nd source/drain pattern and the 1 st portion of the 1 st liner,
wherein the contact structure penetrates the 2 nd liner to contact the 1 st source/drain pattern.
11. The semiconductor device of claim 9 , wherein the contact structure does not penetrate the liner portion of the 1 st liner to contact the 1 st source/drain pattern.
12. The semiconductor device of claim 1 , further comprising a sidewall spacer on only one side surface of the 1 st source/drain pattern among two opposite side surfaces thereof.
13. A semiconductor device comprising:
a 1 st source/drain pattern for a 1 st transistor;
a 2 nd source/drain pattern for a 2 nd transistor, above the 1 st source/drain pattern, the 2 nd source/drain pattern having a smaller width than the 1 st source/drain pattern in a channel-width direction;
a 1 st isolation layer surrounding the 1 st source/drain pattern;
a 2 nd isolation layer surrounding the 2 nd source/drain pattern, the 1 st and 2 nd isolation layers comprising a first material;
a liner surrounding the 1 st source/drain pattern, the liner comprising a 2 nd material; and
a contact structure on the 1 st source/drain pattern,
wherein the contact structure penetrates the 2 nd isolation layer and the liner to contact the 1 st source/drain pattern without penetrating the 1 st isolation layer.
14. The semiconductor device of claim 13 , wherein the 1 st material comprises an oxide material, and the 2 nd material comprises a nitride material.
15. The semiconductor device of claim 13 , wherein the contact structure does not penetrate another layer comprising the 1 st material or the 2 nd material between the 2 nd isolation layer and the liner.
16. The semiconductor device of claim 13 , further comprising a sidewall spacer on only one side surface of the 1 st source/drain pattern among two opposite side surfaces thereof.
17. A method of manufacturing a semiconductor device, the method comprising:
forming a 1 st channel structure and a 2 nd channel structure above the 1 st channel structure such that the 1 st and 2 nd channel structures are extended in a 1 st direction, and the 2 nd channel structure has a smaller width than the 1 st channel structure in a 2 nd direction intersecting the 1 st direction;
forming a 1 st source/drain pattern on the 1 st channel structure;
forming a 1 st liner on the 1 st source/drain pattern;
forming a 1 st isolation layer surrounding the 1 st source/drain pattern with the 1 st liner thereon;
forming a 2 nd source/drain pattern on the 2 nd channel structure;
forming a 2 nd isolation layer surrounding the 2 nd source/drain pattern; and
forming a contact structure such that the contact structure penetrates the 2 nd isolation layer and the liner to contact the 1 st source/drain pattern without penetrating the 1 st isolation layer.
18. The method of claim 17 , wherein the 1 st material comprises an oxide material, and the 2 nd material comprises a nitride material.
19. The method of claim 17 , wherein the contact structure is formed such that the contact structure does not penetrate another layer comprising the 1 st material or the 2 nd material between the 2 nd isolation layer and the liner.
20. The method of claim 17 , further comprising forming a sidewall spacer on only one side surface of the 1 st source/drain pattern among two opposite side surfaces thereof.