Method and structure to improve stacked FET bottom EPI contact
A stacked semiconductor device comprising a lower source/drain epi located on top of a bottom dielectric layer. An isolation layer located on top of the lower source/drain epi and an upper source/drain epi located on top of the isolation layer. A lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi.
1. A stacked semiconductor device comprising:
a lower source/drain epi located on top of a bottom dielectric layer;
an isolation layer located on top of the lower source/drain epi;
an upper source/drain epi located on top of the isolation layer; and
a lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi, wherein the lower electrical contact extends under the lower source/drain epi.
2. The stacked semiconductor device of claim 1 , wherein the one of the multiple side surfaces of the lower source/drain epi that is in contact with the lower electrical contact is a vertical sidewall of the lower source/drain epi.
3. The stacked semiconductor device of claim 1 , wherein the one of the multiple side surfaces of the lower source/drain epi that is in contact with the lower electrical contact is a portion of a bottom surface of the lower source/drain epi.
4. The stacked semiconductor device of claim 1 , wherein a first portion of a bottom surface of the lower source/drain epi is in direct contact with a top surface of a dielectric layer, and wherein a second portion of the bottom surface of the lower source/drain epi is in direct contact with the lower electrical contact.
5. The stacked semiconductor device of claim 4 , wherein the one of the multiple surfaces of the lower source/drain epi that is in contact with the lower electrical contact is a vertical sidewall of the lower source/drain epi.
6. The stacked semiconductor device of claim 5 , wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi is comprised of:
a first contact surface area between the vertical sidewall of the lower source/drain epi connected to the lower electrical contact; and
a second contact surface area between a second portion of the bottom surface of the lower source/drain epi that is connected to the lower electrical contact, wherein a total contact surface area between the lower source/drain epi and the upper source/drain epi is a sum of the first contact surface area and the second contact surface area.
7. The stacked semiconductor device of claim 6 , wherein the first contact surface area is larger than the second contact surface area.
8. The stacked semiconductor device of claim 6 , wherein the first contact surface area is smaller than the second contact surface area.
9. The stacked semiconductor device of claim 6 , wherein the first contact surface area is about equal to the second contact surface area.
10. A stacked semiconductor device comprising:
a lower source/drain epi located on top of a dielectric layer, wherein the lower source/drain epi is comprised of a n-type epi, or a p-type epi;
an isolation layer located on top of the lower source/drain epi and the side of the lower source/drain epi;
an upper source/drain epi located on top of the isolation layer, wherein the upper source/drain epi is comprised of a n-type epi, or a p-type epi;
an interlayer dielectric formed around the upper source/drain epi;
an upper electrical contact that extends through the interlayered dielectric to connect to the upper source/drain epi; and
a lower electrical contact that extends through the interlayer dielectric and the isolation layer to be connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple surfaces of the lower source/drain epi, wherein the lower electrical contact extends under the lower source/drain epi.
11. The stacked semiconductor device of claim 10 , wherein a first portion of the bottom surface of the lower source/drain epi is in direct contact with the top surface of the dielectric layer, and wherein a second portion of the bottom surface of the lower source/drain epi is in direct contact with the lower electrical contact.
12. The stacked semiconductor device of claim 11 , wherein the one of the multiple surfaces of the lower source/drain epi that is in contact with the lower electrical contact is a vertical sidewall of the lower source/drain epi.
13. The stacked semiconductor device of claim 12 , wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi is comprised of:
a first contact surface area that is comprised of the vertical sidewall of the lower source/drain epi that is connected to the lower electrical contact; and
a second contact surface area that is comprised of the second portion of the bottom surface of the lower source/drain epi that is connected to the lower electrical contact, wherein the total contact surface area between the lower source/drain epi and the upper source/drain epi is the sum of the first contact surface area and the second contact surface area.
14. The stacked semiconductor device of claim 13 , wherein the first contact surface area is larger than the second contact surface area.
15. The stacked semiconductor device of claim 13 , wherein the first contact surface area is smaller than the second contact surface area.
16. The stacked semiconductor device of claim 13 , wherein the first contact surface area is about equal to the second contact surface area.