Array of multi-stack nanosheet structures

1. An array of multi-stack transistor structures,

wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array,

wherein each of the multi-stack transistor structures comprises two or more vertically arranged transistor stacks, and

wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

2. The array of multi-stack transistor structures of claim 1 , wherein each of the multi-stack transistor structures comprises:

a 1st transistor stack comprising 1 st and 2 nd source/drain regions;

a 2nd transistor stack formed above the 1 st transistor stack, and comprising 3 rd and 4 th source/drain regions vertically overlapping the 1 st and 2 nd source/drain regions, respectively;

1 st and 2 nd source/drain contact structures landing on side surfaces of the 1st and 2nd source/drain regions, respectively; and

3 rd and 4 th source/drain contact structures landing on top surfaces of the 3 rd and 4 th source/drain regions, respectively.

3. The array of multi-stack transistor structures of claim 2 , wherein at least one of the 1 st and 2 nd source/drain contact structures of at least one of the multi-stack transistor structures in each row contacts the dam structure, and

wherein none of the 3 rd and 4 th source/drain contact structures in each row contacts the dam structure.

4. The array of multi-stack transistor structures of claim 3 , wherein at least one of the multi-stack transistor structures shares at least one of the 1 st to 4 th source/drain region and at least one of the 1 st to 4 th source/drain contact structures with an adjacent multi-stack transistor structure in a same row.

5. The array of multi-stack transistor structures of claim 4 , wherein, except the left-most and right-most multi-stack transistor structures in the same row, at least one of the multi-stack transistor structures in the same row shares the 1 st and 3 rd source/drain regions and the 1 st and 3 rd source/drain contact structures with a multi-stack transistor structure disposed on its left in the same row, and shares the 2 nd and 4 th source/drain regions and the 2 nd and 4 th source/drain contact structures with a multi-stack transistor structure disposed on its right.

6. The array of multi-stack transistor structures of claim 2 , wherein the multi-stack transistor structures in the same row are arranged in a channel length direction, and

wherein at least two of the multi-stack transistor structures in the same row share a same fin region where the 1 st to 4 th source/drain regions and the 3 rd and 4 th source/drain contact structure of the at least two multi-stack transistor structures are disposed in a plan view of the array.

7. The array of multi-stack transistor structures of claim 6 , wherein the multi-stack transistor structures in a same column are arranged in a channel width direction, and shares a same gate structure divided by the dam structure in the plan view of the array.

8. An array of multi-stack transistor structures,

wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array,

wherein each of the multi-stack transistor structures comprises two or more vertically arranged transistor stacks, and

wherein a dam structure is formed between adjacent two rows in a same column and adjacent two columns in a same row so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structures in the other of the adjacent two rows in the same column, and a multi-stack transistor structure in one of the adjacent two columns is electrically isolated from a multi-stack transistor structure in another of the adjacent two columns in the same row.

9. The array of multi-stack transistor structures of claim 8 , wherein each of the multi-stack transistor structures comprises:

a 1 st transistor stack comprising 1 st and 2 nd source/drain regions;

a 2 nd transistor stack formed above the 1 st transistor structure, and comprising 3 rd and 4 th source/drain regions vertically overlapping the 1 st and 2 nd source/drain regions, respectively;

1 st and 2 nd source/drain contact structures landing on side surfaces of the 1 st and 2 nd source/drain regions, respectively; and

3 rd and 4 th source/drain contact structures landing on top surfaces of the 3 rd and 4 th source/drain regions, respectively.