IP Library › Granted Patent US 12,100,755
Granted Patent B2
US 12,100,755 · App. 17/400,076 · Granted Sep 24, 2024

Channel structures including doped 2D materials for semiconductor devices

Inventors: Ching-Hua Lee (Hsinchu, TW); Miao-Syuan Fan (Hsinchu, TW); Ta-Hsiang Kung (New Taipei, TW); Jung-Wei Lee (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/7606H01L21/02568H01L21/0259H01L29/0665H01L29/0673H01L29/1606H01L29/24H01L29/42392H01L29/66969H01L29/78696
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Quick Facts
Patent No.
US 12,100,755
App. No.
17/400,076
Granted
Sep 24, 2024
Kind
B2
Abstract

A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and a gate electrode surrounding the interfacial layer.

Claims (36)

1. A semiconductor device comprising:

a substrate;

a semiconductor structure on the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region, the channel region comprising a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region, wherein the doped 2D material layer does not have a void;

an interfacial layer on the first portion of the doped 2D material layer and on sidewalls of the channel region;

a first semiconductor layer disposed between the first portion of the doped 2D material layer and the interfacial layer, wherein the first semiconductor layer comprises a pristine material, and the pristine material is silicon or silicon germanium; and

a gate electrode on the interfacial layer.

2. The semiconductor device of claim 1 , wherein the doped 2D material layer further comprises a second portion disposed on sidewalls of the channel region, and the first semiconductor layer is on the second portion.

3. The semiconductor device of claim 1 , wherein the doped 2D material layer comprises a graphene material having an n-type dopant or a p-type dopant.

4. The semiconductor device of claim 1 , wherein the doped 2D material layer comprises one of doped WS2, WSe2, MoS2, and MoSe2.

5. The semiconductor device of claim 1 , wherein the channel region is suspended over the substrate, the interfacial layer surrounds the channel region including the first portion of the doped 2D material layer, and the gate electrode surrounds the interfacial layer.

6. The semiconductor device of claim 1 , wherein the first semiconductor layer comprises silicon.

7. The semiconductor device of claim 1 , wherein the first semiconductor layer comprises silicon germanium.

8. The semiconductor device of claim 1 , wherein the doped 2D material layer includes one or more monolayers of 2D material.

9. A semiconductor device comprising:

a substrate;

a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region, the channel region comprising:

a semiconductor layer comprising a pristine material, and the pristine material is silicon or silicon germanium; and

a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the semiconductor layer of the channel region, wherein the doped 2D material layer does not have a void, wherein the doped 2D material layer comprises a first material doped with dopants, and the first material is different from the pristine material of the semiconductor layer;

an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer; and

a gate electrode surrounding the interfacial layer.

10. The semiconductor device of claim 9 , wherein the first portion of the doped 2D material layer extends from the upper surface to a lower surface of the channel region.

11. The semiconductor device of claim 10 , wherein the first portion of the doped 2D material layer has a thickness in a range between 2 nm and 50 nm.

12. The semiconductor device of claim 9 , wherein the doped 2D material layer includes one or more monolayers of 2D material.

13. The semiconductor device of claim 9 , wherein the doped 2D material layer comprises a graphene material having an n-type dopant or a p-type dopant.

14. The semiconductor device of claim 9 , wherein the doped 2D material layer comprises one of doped WS2, WSe2, MoS2, and MoSe2.

15. The semiconductor device of claim 9 , wherein the pristine material is silicon.

16. The semiconductor device of claim 9 , wherein the pristine material is silicon germanium.

17. A semiconductor device, comprising:

a substrate;

a semiconductor structure on the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region;

a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region and a second portion disposed on sidewalls of the channel region, wherein the doped 2D material layer does not have a void;

an interfacial layer on the first portion of the doped 2D material layer and on the second portion of the doped 2D material layer; and

a gate electrode on the interfacial layer.

18. The semiconductor device of claim 17 , wherein a semiconductor layer is disposed between the doped 2D material layer and the interfacial layer.

19. The semiconductor device of claim 17 , wherein the doped 2D material layer includes one or more monolayers of 2D material.

20. The semiconductor device of claim 17 , wherein doped 2D material layer comprises a graphene material having an n-type dopant or a p-type dopant.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2021
From: LEE, CHING-HUA; FAN, MIAO-SYUAN; KUNG, TA-HSIANG; LEE, JUNG-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 057154/0001 →
Continuity (2)
Provisional Application 63173297 · Apr 9, 2021
Related Publication 20220328670A1 · Oct 13, 2022