Semiconductor device and method of fabricating same

1. A semiconductor device, comprising:

a semiconductor substrate including a first region and a second region;

a first interlayer insulating layer covering the second region;

a capping layer disposed on the first interlayer insulating layer, wherein an upper surface of the capping layer includes a first trench;

conductive patterns spaced apart on the capping layer, wherein side surfaces of the conductive patterns are aligned with inner side surfaces of the first trench; and

a peripheral separation pattern disposed in the first trench to cover the side surfaces of the conductive patterns,

wherein the peripheral separation pattern has a first thickness on the side surfaces of the conductive patterns and a second thickness greater than or equal to the first thickness on a lower surface of the first trench.

2. The semiconductor device of claim 1 , wherein an upper surface of the peripheral separation pattern includes a second trench filled with a protection pattern.

3. The semiconductor device of claim 1 , wherein an upper surface of the peripheral separation pattern includes a second trench, and

the semiconductor device further comprises:

an etch stop layer conformally covering the conductive patterns and the peripheral separation pattern; and

a second interlayer insulating layer on the etch stop layer, wherein a portion of the second interlayer insulating layer penetrates into the second trench.

4. The semiconductor device of claim 1 , further comprising:

landing pads disposed on the first region of the semiconductor substrate; and

a landing pad separation pattern filling a space between the landing pads,

wherein the landing pad separation pattern includes a same material as the peripheral separation pattern, the landing pad separation pattern has a first width, and the peripheral separation pattern has a second width greater than the first width.

5. The semiconductor device of claim 4 , wherein the peripheral separation pattern includes a first peripheral sub-insulating pattern, a second peripheral sub-insulating pattern, and a third peripheral sub-insulating pattern, which are sequentially stacked,

the landing pad separation pattern includes a first cell sub-insulating pattern, a second cell sub-insulating pattern, and a third cell sub-insulating pattern, which are sequentially stacked,

the second peripheral sub-insulating pattern includes at least one material having an etch selectivity with respect to the first peripheral sub-insulating pattern and the third peripheral sub-insulating pattern, and

the second cell sub-insulating pattern includes at least one material having an etch selectivity with respect to the first cell sub-insulating pattern and the third cell sub-insulating pattern.

6. The semiconductor device of claim 5 , wherein a thickness of the second peripheral sub-insulating pattern is the same as a thickness of the second cell sub-insulating pattern.

7. The semiconductor device of claim 1 , further comprising:

a bit line on the semiconductor substrate crossing the first region;

a first bit line capping pattern on the bit line; and

a second bit line capping pattern on the first bit line capping pattern,

wherein a thickness of the second bit line capping pattern is the same as a thickness of the capping layer.

8. The semiconductor device of claim 7 , further comprising:

a peripheral gate capping pattern on the second region and covered by the first interlayer insulating layer; and

a peripheral gate electrode below the peripheral gate capping pattern,

wherein a thickness of the peripheral gate capping pattern is the same as a thickness of the first bit line capping pattern.

9. The semiconductor device of claim 7 , further comprising:

a first spacer covering a side surface of the bit line; and

a second spacer covering a side surface of the first bit line capping pattern,

wherein a lower surface of the second spacer contacts an upper surface of the first spacer, and a width of the second spacer is less than a width of the first spacer.

10. A semiconductor device, comprising:

a semiconductor substrate including a cell array region and a peripheral region;

a bit line on the semiconductor substrate crossing the cell array region;

a bit line capping pattern on the bit line;

a landing pad on the bit line capping pattern and electrically isolated from the bit line;

a landing pad separation pattern contacting a side surface of the landing pad;

a first interlayer insulating layer covering the peripheral region;

a capping layer on the first interlayer insulating layer, wherein an upper surface of the capping layer includes a first trench;

conductive patterns spaced apart on the capping layer, wherein side surfaces of the conductive patterns are aligned with inner side surfaces of the first trench; and

a peripheral separation pattern filling the first trench to cover the side surfaces of the conductive patterns,

wherein the peripheral separation pattern has a first thickness on the side surfaces of the conductive patterns, and a second thickness greater than or equal to the first thickness on a lower surface of the first trench.

11. The semiconductor device of claim 10 , wherein an upper surface of the peripheral separation pattern includes a second trench, and the semiconductor device further comprises a protection pattern filling the second trench.

12. The semiconductor device of claim 10 , wherein an upper surface of the peripheral separation pattern includes a second trench, and the semiconductor device further comprises:

an etch stop layer conformally covering the conductive patterns and the peripheral separation pattern; and

a second interlayer insulating layer on the etch stop layer, wherein a portion of the second interlayer insulating layer penetrates into a region between the conductive patterns.

13. The semiconductor device of claim 10 , further comprising:

a peripheral gate capping pattern, having a third thickness, disposed on the peripheral region and covered by the first interlayer insulating layer; and

a peripheral gate electrode, having a fourth thickness, disposed below the peripheral gate capping pattern,

wherein a thickness of the bit line capping pattern is equal to a sum of the third thickness and a thickness of the capping layer.

14. The semiconductor device of claim 13 , wherein a thickness of the bit line is equal to a thickness of the peripheral gate electrode.

15. The semiconductor device of claim 10 , wherein the landing pad separation pattern and the peripheral separation pattern include a same material,

the landing pad separation pattern has a first width, and

the peripheral separation pattern has a second width greater than the first width.

16. The semiconductor device of claim 15 , wherein the first thickness is greater than or equal to half of the first width and is less than half of the second width.