Memory programming techniques to reduce power consumption
View Patent ↗A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
1. A method of programming a memory device using a single-level cell (SLC) programming operation, wherein the memory device includes a plurality of dies, a plurality of planes, a plurality of strings, and a plurality of word lines, the method comprising the steps of:
in response to an SLC program command to perform the SLC programming operation on a plurality of memory cells including a first set of memory cells in a first plane of the plurality of planes and a second set of memory cells in a second plane of the plurality of planes:
as a step in the SLC programming operation, making a determination of which of the first plane and the second plane to perform a verify operation on;
as a step in the SLC programming operation and in response to the determination, programming only a single bit of data into each memory cell of the first set of memory cells in the first plane using a first programming operation that includes a single programming pulse and no verify pulse; and
as a step in the SLC programming operation, in response to the determination, and subsequent to the first programming operation, programming only a single bit of data into each memory cell of the second set of memory cells in the second plane using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
2. The method as set forth in claim 1 wherein the first set of memory cells is approximately equal in number to the second set of memory cells.
3. The method as set forth in claim 1 , wherein for each combination of die and plane and word line, the memory cells coupled with at least half of the strings are of the first set of memory cells that are programmed using the first programming operation that includes the single programming pulse and no verify pulse.
4. The method as set forth in claim 3 wherein a predetermined pattern establishes which memory cells are included in the first set of memory cells that are programmed using the first programming operation that includes the single programming pulse and no verify pulse and which memory cells are included in the second set of memory cells that are programmed using the second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
5. The method as set forth in claim 1 wherein each plane includes five strings which are located between two slit etches.
6. The method as set forth in claim 5 wherein the first set of memory cells that are programmed using the first programming operation that includes the single programming pulse and no verify pulse include the memory cells that are coupled to the strings that are immediately adjacent the slit etches.
7. The method as set forth in claim 6 wherein the first set of memory cells that are programmed using the first programming operation that includes the single programming pulse and no verify pulse further includes the memory cells that are coupled to a middle string that is spaced equally between the two slit etches.
8. A memory device, comprising:
a plurality of dies, a plurality of planes, a plurality of strings, and a plurality of word lines;
a plurality of memory cells including a first set of memory cells in a first plane of the plurality of planes and a second set of memory cells in a second plane of the plurality of planes; and
control circuitry configured to program a single bit of data into each memory cell of the plurality of memory cells using a single-level cell (SLC) programming operation, the control circuitry being further configured to, in response to an SLC program command to perform the SLC programming operation on the plurality of memory cells,
make a determination of which of the first plane and the second plane to perform a verify operation on,
in the SLC programming operation and in response to the determination, program only a single bit of data into each memory cell of the first set of memory cells in the first plane using a first programming operation that includes a single programming pulse and no verify pulse, and
in the SLC programming operation, in response to the determination, and subsequent to the first programming operation, program only a single bit of data into each memory cell of the second set of memory cells in the second plane using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
9. The memory device as set forth in claim 8 wherein the first set of memory cells is approximately equal in number to the second set of memory cells.
10. The memory device as set forth in claim 8 wherein for each combination of die and word line, the memory cells coupled with at least half of the strings are of the first set of memory cells that are programmed by the control circuitry using the first programming operation that includes the single programming pulse and no verify pulse.
11. The memory device as set forth in claim 10 wherein a predetermined pattern establishes which memory cells are included in the first set of memory cells that are programmed by the control circuitry using the first programming operation that includes the single programming pulse and no verify pulse and which memory cells are included in the second set of memory cells that are programmed by the control circuitry using the second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
12. The memory device as set forth in claim 8 wherein each plane includes five strings which are located between two slit etches.
13. The memory device as set forth in claim 12 wherein the first set of memory cells that are programmed by the control circuitry using the first programming operation that includes the single programming pulse and no verify pulse include the memory cells that are coupled to the strings that are immediately adjacent the slit etches.
14. The memory device as set forth in claim 13 wherein the first set of memory cells that are programmed by the control circuitry using the first programming operation that includes the single programming pulse and no verify pulse further includes the memory cells that are coupled to a middle string that is spaced equally between the two slit etches.
15. An apparatus including a memory device, the memory device including a plurality of dies, a plurality of planes, a plurality of strings, and a plurality of word lines, the apparatus comprising:
a non-volatile memory including a programming means for programming, using a single-level cell (SLC) programming operation, a single bit of data into each memory cell of a plurality of memory cells including a first set of memory cells in a first plane of the plurality of planes and a second set of memory cells in a second plane of the plurality of planes, the programming means being further configured to, in response to an SLC program command to perform the SLC programming operation on the plurality of memory cells,
make a determination of which of the first plane and the second plane to perform a verify operation on,
in the SLC programming operation and in response to the determination, program only a single bit of data into each memory cell of the first set of memory cells in the first plane using a first programming operation that includes a single programming pulse and no verify pulse, and
in the SLC programming operation, in response to the determination, and subsequent to the first programming operation, program only a single bit of data into each memory cell of the second set of memory cells in the second plane using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
16. The apparatus as set forth in claim 15 wherein the first set of memory cells is approximately equal in number to the second set of memory cells.
17. The apparatus as set forth in claim 15 wherein for each combination of die and word line, the memory cells coupled with at least half of the strings are of the first set of memory cells that are programmed by the control circuitry using the first programming operation that includes the single programming pulse and no verify pulse.