IP Library Granted Patent US 12,315,760
Granted Patent B2
US 12,315,760 · App. 17/435,630 · Granted May 27, 2025

Method for manufacturing electronic component device

Inventors: Tomoaki Shibata (Tokyo, JP); Tsuyoshi Ogawa (Tokyo, JP); Xinrong Li (Tokyo, JP)
Assignee: RESONAC CORPORATION
H01L21/76817H01L21/76877
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Quick Facts
Patent No.
US 12,315,760
App. No.
17/435,630
Granted
May 27, 2025
Kind
B2
Abstract

Disclosed is a method for manufacturing an electronic component including: forming a via hole extending in a thickness direction of a curable sealing resin layer provided on a base material by an imprint method of pressing a mold into the sealing resin layer from a side opposite to the base material; curing the sealing resin layer; filling the via hole with a conductor precursor; and forming a conductive via by heating the conductor precursor filled in the via hole.

Claims (26)

1. A method for manufacturing an electronic component device, the method comprising:

forming a via hole extending in a thickness direction of a curable sealing resin layer provided on a base material by an imprint method of pressing a mold into the sealing resin layer from a side opposite to the base material, wherein a semiconductor element is provided on the base material, and the semiconductor element is sealed by the sealing resin layer;

curing the sealing resin layer;

filling the via hole with a conductor precursor; and

forming a conductive via by heating the conductor precursor filled in the via hole, wherein the via hole has a depth of 30 to 500 μm.

2. The method according to claim 1 , wherein a ratio of the depth of the via hole to a maximum width of the via hole is 1 or more.

3. The method according to claim 2 , wherein the ratio of the depth of the via hole to the maximum width of the via hole is 10 or less.

4. The method according to claim 1 , wherein a ratio of the depth of the via hole to a maximum width of the via hole is 2 or more.

5. The method according to claim 4 , wherein the ratio of the depth of the via hole to the maximum width of the via hole is 10 or less.

6. The method according to claim 4 , wherein the maximum width of the via hole is 10 to 200 μm.

7. The method according to claim 1 , wherein the curable sealing resin layer is cured prior to filling the via hole with the conductor precursor.

8. A method for manufacturing an electronic component device, the method comprising:

forming a via hole extending in a thickness direction of a curable sealing resin layer provided on a base material by an imprint method of pressing a mold into the sealing resin layer from a side opposite to the base material, wherein a semiconductor element is provided on the base material, and the semiconductor element is sealed by the sealing resin layer;

curing the sealing resin layer;

filling the via hole with a conductor precursor, wherein the conductor precursor comprises a plurality of metallic particles and an organic binder in which the plurality of metallic particles are dispersed; and

forming a conductive via by heating the conductor precursor filled in the via hole, wherein the via hole has a depth of 30 to 500 μm, wherein when the conductor precursor is heated, the plurality of metallic particles form a metallic sintered body through transitional liquid phase sintering, thereby forming the conductive via comprising the metallic sintered body.

9. A method for manufacturing an electronic component device, the method comprising:

forming a via hole extending in a thickness direction of a curable sealing resin layer provided on a base material by an imprint method of pressing a mold into the sealing resin layer from a side opposite to the base material;

curing the sealing resin layer;

filling the via hole with a conductor precursor, wherein the conductor precursor comprises a plurality of metallic particles and an organic binder in which the plurality of metallic particles are dispersed, and the organic binder comprises a thermoplastic resin having a polyoxyalkylene group or a polysiloxane group; and

forming a conductive via by heating the conductor precursor filled in the via hole, wherein the via hole has a depth of 30 to 500 μm.

10. A method for manufacturing an electronic component device, the method comprising:

forming a via hole extending in a thickness direction of a curable sealing resin layer provided on a base material by an imprint method of pressing a mold into the sealing resin layer from a side opposite to the base material;

filling the via hole with a conductor precursor;

curing the sealing resin layer, wherein the sealing resin layer is cured after filling the via hole with the conductor precursor; and

forming a conductive via by heating the conductor precursor filled in the via hole, wherein the via hole has a depth of 30 to 500 μm.

Assignments (3)
CHANGE OF ADDRESS Recorded Feb 9, 2024
From: RESONAC CORPORATION
To: RESONAC CORPORATION
Reel/Frame 066547/0677 →
CHANGE OF NAME Recorded Mar 8, 2023
From: SHOWA DENKO MATERIALS CO., LTD.
To: RESONAC CORPORATION
Reel/Frame 062992/0805 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2021
From: SHIBATA, TOMOAKI; OGAWA, TSUYOSHI; LI, XINRONG
To: SHOWA DENKO MATERIALS CO., LTD.
Reel/Frame 057928/0261 →
Priority Claims (1)
JP 2019-040656 · Mar 6, 2019 · national
Continuity (1)
Related Publication 20220148914A1 · May 12, 2022
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