Microelectronic devices including two-dimensional materials, and related memory devices and electronic systems
A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.
1. A microelectronic device, comprising:
discrete dielectric structures overlying an isolation structure and separated from one another by filled trenches;
a non-planar 2D material structure extending over surfaces of the isolation structure and the discrete dielectric structures inside and outside of the filled trenches, the non-planar 2D material structure comprising:
conductively doped regions; and
channel regions between the conductively doped regions;
gate structures overlying and substantially aligned with the channel regions of the non-planar 2D material structure;
conductive structures extending from the gate structures and into the filled trenches;
contact structures coupled to some of the conductively doped regions and extending into the isolation structure; and
at least one additional contact structure coupled to at least one other of the conductively doped regions and extending away from the isolation structure.
2. The microelectronic device of claim 1 , wherein the non-planar 2D material structure physically contacts and conforms to the surfaces of the isolation structure and the discrete dielectric structures inside and outside of the filled trenches.
3. The microelectronic device of claim 1 , wherein the non-planar 2D material structure further comprises additional conductively doped regions between the channel regions and the conductively doped regions, the additional conductively doped regions comprising relatively smaller amounts of conductive dopants than the conductively doped regions.
4. The microelectronic device of claim 3 , wherein:
the conductively doped regions of the non-planar 2D material structure comprise N + regions; and
the additional conductively doped regions of the non-planar 2D material structure comprise N − regions.
5. The microelectronic device of claim 3 , wherein the contact structures and the at least one additional contact structure physically contact one or more of the conductively doped regions and the additional conductively doped regions of the non-planar 2D material structure.
6. The microelectronic device of claim 1 , wherein:
the conductively doped regions of the non-planar 2D material structure comprise at least one source region and at least two drain regions;
the contact structures comprise at least two local contact structures coupled to the at least two drain regions; and
the at least one additional contact structure comprises at least one global contact structure coupled to the at least one source region.
7. The microelectronic device of claim 1 , wherein:
the conductively doped regions comprise source regions and drain regions;
the channel regions are interposed between the source regions and the drain regions; and
the non-planar 2D material structure further comprises lateral double-diffused regions interposed between the channel regions and the source regions and the drain regions.
8. The microelectronic device of claim 1 , wherein the gate structures and the discrete dielectric structures horizontally extend orthogonal to one another.
9. The microelectronic device of claim 1 , wherein the non-planar 2D material structure comprises a transition metal di-chalcogenide having a general chemical formula MX 2 , wherein M is selected from Mo, W, Nb, Zr, Hf, Re, Pt, Ti, Ta, V, Co, Cd, Cr, and wherein X is selected from S, Se, and Te.
10. The microelectronic device of claim 1 , wherein the non-planar 2D material structure comprises a carbide or carbonitride having a general chemical formula M n+1 X n , wherein M is selected from Ti, Hf, Zr, V, Nb, Ta, and wherein X is selected from C and N.
11. A memory device, comprising:
a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers;
a staircase structure at a horizontal end the stack structure, the staircase structure having steps comprising edges of the tiers;
a string driver transistor vertically overlying the staircase structures and comprising:
a channel region comprising at least one 2D material;
lateral double-diffused regions horizontally neighboring the channel region and comprising the at least one 2D material; and
source and drain regions horizontally neighboring the lateral double-diffused regions and comprising the at least one 2D material;
at least one additional conductive structure extending from and between the string driver transistor and one of the steps of the staircase structure; and
a string of memory cells vertically extending through the stack structure.
12. The memory device of claim 11 , wherein the at least one 2D material has a bandgap within a range of from about 1.2 eV to about 2.5 eV, and has electron mobility within a range of from about 10 cm 2 /V·s to about 400 cm 2 /V·s.
13. The memory device of claim 11 , wherein the at least one 2D material has a substantially non-planar shape conforming to a combined topography of dielectric fin structures and an insolation structure vertically underlying the at least one 2D material.
14. The memory device of claim 11 , wherein the at least one 2D material has a substantially horizontally planar shape.
15. The memory device of claim 11 , wherein the at least one additional conductive structure comprises:
a vertical contact structure on one of the steps of the staircase structure; and
a local contact structure vertically extending downward from the string driver transistor and electrically coupled to the vertical contact structure.
16. The memory device of claim 15 , wherein the at least one additional conductive structure further comprises another conductive structure vertically between and in physical contact with the vertical contact structure and the local contact structure.
17. The memory device of claim 15 , further comprising global contact structures vertically extending upward from the string driver transistor.
18. An electronic system, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device and comprising:
a stack structure having tiers comprising conductive structures and insulating structures vertically neighboring the conductive structures, the stack structure comprising:
a staircase region comprising staircase structures having steps comprising horizontal ends of the tiers; and
a memory array region horizontally neighboring the staircase region;
contact structures on the steps of the staircase structures;
a microelectronic device electrically coupled to the contact structures and comprising transistors vertically overlying and within horizontal boundaries of the staircase region of the stack structure, each of the transistors comprising:
a channel region comprising a 2D material;
conductively doped regions neighboring opposing horizontal boundaries of the channel region and comprising the 2D material doped with at least one conductive dopant; and
a gate structure vertically overlying and at least partially horizontally aligned with the channel region; and
vertically extending strings of memory cells within the memory array region of the stack structure.
19. The electronic system of claim 18 , wherein the memory device comprises a 3D NAND Flash memory device.