IP Library › Granted Patent US 12,382,712
Granted Patent B2
US 12,382,712 · App. 17/448,738 · Granted Aug 5, 2025

Semiconductor dies and devices with frontside and backside coils for inductive coupling

Inventors: Peter Baumgartner (Munich, DE); Joachim Assenmacher (Unterhaching, DE); Walther Lutz (Erding, DE); Martin Ostermayr (Woerth, DE); Georg Seidemann (Landshut, DE)
Assignee: Intel Corporation
H10D84/40H01L23/5227H01L23/53257H10D1/20
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Quick Facts
Patent No.
US 12,382,712
App. No.
17/448,738
Granted
Aug 5, 2025
Kind
B2
Abstract

A semiconductor die is disclosed, including a plurality of transistors at a frontside of a semiconductor substrate, a backside inductor at a backside of the semiconductor substrate; and a frontside inductor at the frontside of the semiconductor substrate. The frontside inductor and the backside inductor are inductively coupled.

Claims (42)

1. A semiconductor die, comprising:

a plurality of transistors at a frontside of a semiconductor substrate,

a backside inductor at a backside of the semiconductor substrate; and

a frontside inductor at the frontside of the semiconductor substrate, wherein the frontside inductor and the backside inductor are configured to be inductively coupled,

wherein at least a part of the frontside inductor is formed by an electrically conductive line extending into the semiconductor substrate.

2. The semiconductor die of claim 1 , wherein at least a part of the frontside inductor is formed by an electrically conductive line arranged vertically between a gate of a transistor of the plurality of transistors and the semiconductor substrate.

3. The semiconductor die of claim 1 , wherein the frontside inductor has a single winding.

4. The semiconductor die of claim 1 , wherein at least a part of the frontside inductor is formed by a metal line arranged above the plurality of transistors.

5. The semiconductor die of claim 1 , wherein the frontside inductor is electrically connected to a source region or a drain region of a transistor of the plurality of transistors.

6. The semiconductor die of claim 1 , wherein a material of the frontside inductor and the backside inductor includes metal.

7. The semiconductor die of claim 1 , further comprising:

circuitry which includes the plurality of transistors,

wherein the semiconductor die is configured to provide at least one of: a power supply signal, a data signal, or a clock signal from the backside inductor through inductive coupling to the frontside inductor and from the frontside inductor to the circuitry.

8. The semiconductor device of claim 7 , wherein the circuitry is configured to be unlocked by at least one of the data signal, the power supply signal, or the clock signal.

9. The semiconductor die of claim 1 , wherein the electrically conductive line includes at least one of tungsten or ruthenium.

10. The semiconductor die of claim 1 , wherein the backside inductor includes at least one winding forming an open loop in a plane at the backside.

11. The semiconductor die of claim 1 , wherein the backside inductor is electrically connected to a second backside inductor at the backside of the semiconductor substrate,

wherein the second backside inductor is configured to inductively couple to an external inductor or a second frontside inductor at the frontside of the semiconductor substrate.

12. The semiconductor die of claim 1 , wherein the backside inductor is formed in a plurality of layers of metallizations.

13. The semiconductor die of claim 1 , wherein the backside inductor includes at least one winding.

14. The semiconductor die of claim 1 , wherein the transistors are FinFETs.

15. An electronic device comprising:

a circuit board including a circuit board inductor; and

a semiconductor die including a die inductor and circuitry,

wherein the electronic device is configured to provide a power supply signal, a data signal or a clock signal from the circuit board inductor through inductive coupling to the die inductor and from the die inductor to the circuitry.

16. The electronic device of claim 15 , wherein the circuitry includes a plurality of transistors at a frontside of a semiconductor substrate, and

wherein the die inductor is arranged at a backside of the semiconductor substrate.

17. A semiconductor die, comprising:

a plurality of transistors at a frontside of a semiconductor substrate,

a backside coil at a backside of the semiconductor substrate, and

a frontside coil at the frontside of the semiconductor substrate,

wherein the frontside coil includes at least one winding, the backside coil includes at least one winding, and

wherein at least a part of the frontside coil is formed by an electrically conductive line extending into the semiconductor substrate.

18. The semiconductor die of claim 17 , wherein:

the frontside coil is electrically connected to a source region or a drain region of a transistor of the plurality of transistors.

19. A method of forming a semiconductor die, comprising:

forming a plurality of transistors at a frontside of a semiconductor substrate,

forming a frontside inductor at the frontside of the semiconductor substrate, and forming a backside inductor at a backside of the semiconductor substrate;

wherein the frontside inductor and the backside inductor are configured to be inductively coupled,

wherein at least a part of the frontside inductor is formed by an electrically conductive line extending into the semiconductor substrate.

20. The method of forming a semiconductor die of claim 19 , further comprising:

forming at least a part of the frontside inductor by an electrically conductive line arranged vertically between a gate of a transistor of the plurality of transistors and the semiconductor substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076063/0964 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2021
From: BAUMGARTNER, PETER; ASSENMACHER, JOACHIM; LUTZ, WALTHER; OSTERMAYR, MARTIN; SEIDEMANN, GEORG
To: INTEL CORPORATION
Reel/Frame 058193/0797 →
Continuity (1)
Related Publication 20230101378A1 · Mar 30, 2023
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