Silicon carbide field-effect transistors
In a general aspect, a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) can include a substrate of a first conductivity type, a drift region of the first conductivity type disposed on the substrate, a spreading layer of the first conductivity type disposed in the drift region, a body region of a second conductivity type disposed in the spreading layer, and a source region of the first conductivity type disposed in the body region. The SiC MOSFET can also include a gate structure that includes a gate oxide layer, an aluminum nitride layer disposed on the gate oxide layer, and a gallium nitride layer of the second conductivity disposed on the aluminum nitride layer.
1. A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:
a SiC substrate of a first conductivity type;
a drift region of the first conductivity type disposed on the SiC substrate;
a spreading layer of the first conductivity type disposed in the drift region;
a body region of a second conductivity type disposed in the spreading layer;
a source region of the first conductivity type disposed in the body region; and
a gate structure including:
a gate oxide layer;
an aluminum nitride (AlN) layer disposed on the gate oxide layer; and
a gallium nitride (GaN) layer of the second conductivity type disposed on the AlN layer.
2. The SiC MOSFET of claim 1 , wherein the drift region has a thickness of approximately 9.5 micrometers.
3. The SiC MOSFET of claim 1 , wherein the drift region has a doping concentration of 1×10 16 cm −3 .
4. The SiC MOSFET of claim 1 , wherein the drift region is an epitaxial SiC drift region.
5. The SiC MOSFET of claim 1 , wherein the gate oxide layer has a thickness between 25 nanometers (nm) and 100 nm.
6. The SiC MOSFET of claim 1 , further comprising:
an Ohmic drain contact disposed on the SiC substrate;
an interlayer dielectric disposed on the gate structure;
a source metal structure including:
an Ohmic contact layer, the Ohmic contact layer defining:
an Ohmic contact to the body region; and
an Ohmic contact to the source region; and
a metal layer disposed on the Ohmic contact, a portion of the source region and the interlayer dielectric, the gate structure being electrically isolated from the metal layer by the interlayer dielectric.
7. The SiC MOSFET of claim 6 , wherein the Ohmic contact to the body region includes a subcontact region of the second conductivity type disposed in the body region, the subcontact region having a doping concentration that is higher than a doping concentration of the body region.
8. The SiC MOSFET of claim 7 , wherein the Ohmic contact layer is in contact with the subcontact region and the source region.
9. The SiC MOSFET of claim 6 , further comprising a drain metal layer disposed on the Ohmic drain contact.
10. The SiC MOSFET of claim 1 , further comprising a nitrided interface between the gate oxide layer and the spreading layer, and between the gate oxide layer and the source region.
11. The SiC MOSFET of claim 1 , wherein the GaN layer is crystalline or microcrystalline.
12. The SiC MOSFET of claim 1 , wherein the AlN layer is atomic layer deposited.
13. A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:
an n-type SiC substrate;
an n-type drift region disposed on the n-type SiC substrate;
an n-type spreading layer disposed in the drift region;
a p-type body region disposed in the spreading layer;
an n-type source region disposed in the body region; and
a gate structure including:
a gate oxide layer;
an aluminum nitride (AlN) layer disposed on the gate oxide layer; and
a p-type gallium nitride (GaN) layer disposed on the AlN layer.
14. The SiC MOSFET of claim 13 , further comprising a nitrided interface between the gate oxide layer and the n-type spreading layer, and between the gate oxide layer and the n-type source region.
15. The SiC MOSFET of claim 13 , wherein the n-type drift region has a thickness of approximately 9.5 micrometers.
16. The SiC MOSFET of claim 13 , wherein the n-type drift region has a doping concentration of 1×10 16 cm −3 .
17. The SiC MOSFET of claim 13 , wherein the gate oxide layer has a thickness between 25 nanometers (nm) and 100 nm.
18. The SiC MOSFET of claim 13 , further comprising:
an Ohmic drain contact disposed on the n-type SiC substrate;
an interlayer dielectric disposed on the gate structure;
a source metal structure including:
an Ohmic contact layer, the Ohmic contact layer defining:
an Ohmic contact to the p-type body region; and
an Ohmic contact to the n-type source region; and
a metal layer disposed on the Ohmic contact, a portion of the n-type source region and the interlayer dielectric, the gate structure being electrically isolated from the metal layer by the interlayer dielectric.
19. The SiC MOSFET of claim 18 , wherein the Ohmic contact to the body region includes a p-type subcontact region disposed in the p-type body region, the p-type subcontact region having a doping concentration that is higher than a doping concentration of the p-type body region.
20. The SiC MOSFET of claim 19 , wherein the Ohmic contact layer is in contact with the p-type subcontact region and the n-type source region.