Damascene interconnect spacer to facilitate gap fill
A semiconductor component includes a dielectric layer including an opening. The semiconductor component further includes a liner arranged in the opening in direct contact with the dielectric layer. The semiconductor component further includes a wetting layer arranged in the opening in direct contact with the liner. The semiconductor component further includes an interconnect structure arranged in the opening in direct contact with the wetting layer. The semiconductor component further includes a cap arranged in the opening in direct contact with the interconnect structure and separated from the wetting layer by a spacer.
1. A semiconductor component, comprising:
a dielectric layer including an opening;
a liner arranged in the opening in direct contact with the dielectric layer;
a wetting layer arranged in the opening in direct contact with the liner;
an interconnect structure arranged in the opening in direct contact with the wetting layer; and
a cap arranged in the opening in direct contact with the interconnect structure and separated from the wetting layer by a spacer, wherein a lowermost surface of the spacer is in direct contact with an uppermost surface of the wetting layer.
2. The semiconductor component of claim 1 , wherein an uppermost surface of the liner is substantially coplanar with an uppermost surface of the spacer.
3. The semiconductor component of claim 2 , wherein the uppermost surface of the liner and the uppermost surface of the spacer are substantially coplanar with the uppermost surface of the wetting layer.
4. The semiconductor component of claim 2 , wherein the uppermost surface of the liner and the uppermost surface of the spacer are arranged higher than the uppermost surface of the wetting layer.
5. The semiconductor component of claim 1 , wherein an uppermost surface of the cap is substantially coplanar with an uppermost surface of the liner and an uppermost surface of the spacer.
6. The semiconductor component of claim 5 , wherein the uppermost surface of the cap is substantially coplanar with the uppermost surface of the wetting layer.
7. The semiconductor component of claim 5 , wherein the uppermost surface of the cap is arranged higher than the uppermost surface of the wetting layer.
8. The semiconductor component of claim 1 , wherein:
the wetting layer is made of ruthenium; and
the cap is made of cobalt.
9. The semiconductor component of claim 1 , wherein the spacer is made of a metal nitride.
10. The semiconductor component of claim 1 , wherein the spacer is integrally formed with the liner.
11. The semiconductor component of claim 1 , wherein the wetting layer is interposed between the liner and the spacer.
12. The semiconductor component of claim 1 , wherein the cap is not in direct contact with the wetting layer.
13. The semiconductor component of claim 1 , wherein:
a first side surface of the wetting layer is in direct contact with the liner; and
a second side surface of the wetting layer is opposite the first side surface of the wetting layer and is in direct contact with the spacer.
14. A method of making a semiconductor component, the method comprising:
forming a liner in an opening in a dielectric layer;
forming a wetting layer in the opening in direct contact with the liner;
forming an interconnect structure in the opening in direct contact with the wetting layer;
recessing the interconnect structure and the wetting layer relative to the dielectric layer;
forming a spacer on top of the wetting layer and in direct contact with the liner; and
forming a cap on top of the interconnect structure and in direct contact with the spacer such that the cap is not in direct contact with the wetting layer.
15. The method of claim 14 , wherein forming the spacer includes:
depositing a layer of spacer material on top of the liner, the wetting layer, and the interconnect structure; and
selectively removing the layer of spacer material from on top of the liner and the interconnect structure.
16. The method of claim 14 , wherein:
recessing the interconnect structure and the wetting layer includes recessing the liner relative to the dielectric layer; and
forming the spacer includes:
depositing a layer of spacer material on top of the liner, the wetting layer, and the interconnect structure; and
selectively removing the layer of spacer material from on top of the interconnect structure.
17. A method of making a semiconductor component, the method comprising:
forming a liner in an opening in a dielectric layer;
forming a wetting layer in the opening in direct contact with the liner;
forming an interconnect structure in the opening in direct contact with the wetting layer;
recessing the interconnect structure relative to the dielectric layer;
forming a spacer on top of the interconnect structure and in direct contact with the wetting layer, wherein a lowermost surface of the spacer is in direct contact with an uppermost surface of the wetting layer; and
forming a cap on top of the interconnect structure and in direct contact with the spacer such that the cap is not in direct contact with the wetting layer.
18. The method of claim 17 , wherein forming the spacer includes:
depositing a layer of spacer material on top of the liner, the wetting layer, and the interconnect structure; and
selectively removing the layer of spacer material from on top of the liner, the wetting layer, and a portion of the interconnect structure.
19. The method of claim 18 , wherein forming the cap includes depositing a layer of cap material on the portion of the interconnect structure from which the layer of spacer material was selectively removed.