Semiconductor devices and methods of manufacturing thereof

1. A semiconductor device, comprising:

a plurality of channel layers vertically spaced from one another;

a gate structure wrapping around each of the plurality of channel layers;

an inner spacer that is disposed along sidewalls of a lower portion of the gate structure; and

an epitaxial structure electrically coupled to the plurality of channel layers;

wherein the epitaxial structure contacts a sidewall, a portion of a top surface, and a portion of a bottom surface of each of the plurality of channel layers, and wherein the inner spacer curves toward the lower portion of the gate structure, and wherein a sidewall of the epitaxial structure curves with the inner spacer toward the lower portion of the gate structure.

2. The semiconductor device of claim 1 , further comprising:

a gate spacer that is disposed along sidewalls of an upper portion of the gate structure.

3. The semiconductor device of claim 2 , wherein the inner spacer includes a plurality of portions, each of which is disposed between neighboring ones of the plurality of channel layers.

4. The semiconductor device of claim 2 , wherein the gate structure is electrically isolated from the epitaxial structure through at least one of the gate spacer or the inner spacer.

5. The semiconductor device of claim 2 , wherein each of the channel layers laterally protrudes from at least one of the gate spacer or the inner spacer.

6. The semiconductor device of claim 2 , wherein a thickness of the gate spacer decreases with an increasing height of the gate spacer.

7. The semiconductor device of claim 1 , wherein a sidewall of the epitaxial structure contacting the plurality of channel layers presents a square-wave profile.

8. The semiconductor device of claim 1 , wherein the plurality of channel layers extend along a first direction and the gate structures extends along a second direction perpendicular to the first direction, and wherein the epitaxial structure is disposed on a side of the channel layers along the first direction.

9. A semiconductor device, comprising:

a substrate;

a plurality of channel layers that are disposed above the substrate and extend along a first direction;

a metal gate structure that extends along a second direction perpendicular to the first direction and wraps around each of the plurality of channel layers;

a gate spacer disposed along an upper portion of the metal gate structure;

an inner spacer disposed along a lower portion of the metal gate structure; and

a source/drain structure disposed along the metal gate structure, with the gate spacer and the inner spacer disposed therebetween;

wherein each of the plurality of channel layers extends toward the source/drain structure beyond a sidewall of the gate spacer and a sidewall of the inner spacer that contact the source/drain structure, wherein the inner spacer curves toward the metal gate structure, and wherein a sidewall of the source/drain structure curves with the inner spacer toward the metal gate structure.

10. The semiconductor device of claim 9 , wherein the inner spacer comprises a plurality of portions, and each of the plurality of portions is vertically disposed between neighboring ones of the plurality of channel layers.

11. The semiconductor device of claim 9 , wherein each of the channel layers has a sidewall facing the second direction, and wherein the sidewalls of the channel layers, the sidewall of the gate spacer, and the sidewall of the inner spacer collectively present a square-wave profile.

12. The semiconductor device of claim 9 , wherein the sidewall of the gate spacer is perpendicular to a top surface of the substrate.

13. The semiconductor device of claim 9 , wherein the sidewall of the gate spacer is tilted toward a sidewall of the metal gate structure, with an increasing height of the metal gate structure.

14. The semiconductor device of claim 9 , wherein the sidewall of the inner spacer has a curvature-based profile.

15. The semiconductor device of claim 9 , wherein each of the plurality of channel layers protrudes beyond the sidewall of the gate spacer and the sidewall of the inner spacer with a distance that ranges between about 0.3 nanometers (nm) and about 20 nm.

16. The semiconductor device of claim 9 , wherein the source/drain structure contacts a lower portion of the sidewall of the gate spacer, the sidewall of the inner spacer, the sidewalls of the channel layers, a portion of a top surface of each of the channel layers, and a portion of a bottom surface of each of the channel layers.

17. A method for making a semiconductor device, comprising:

forming a fin structure over a substrate, wherein the fin structure comprises a plurality of channel layers and a plurality of sacrificial layers alternately stacked on top of one another;

forming a dummy gate structure straddling the fin structure;

removing an upper portion of the fin structure that laterally protrudes from the dummy gate structure;

removing respective end portions of the plurality of sacrificial layers;

forming an inner spacer comprising a plurality of portions, each of which extends along a sidewall of each of the plurality of sacrificial layers, wherein the plurality of channel layers laterally protrude from an exposed sidewall of the inner spacer; and

forming a source/drain structure coupled to the plurality of channel layers, with the inner spacer disposed therebetween,

wherein the inner spacer curves toward the dummy gate structure, and wherein a sidewall of the source/drain structure curves with the inner spacer toward the dummy gate structure.

18. The method of claim 17 , wherein the step of forming an inner spacer further comprises:

depositing a dielectric layer extending along a sidewall of the fin structure, thereby filling up the removed end portions of the sacrificial layers; and

etching the dielectric layer until the exposed sidewall of the inner spacer inwardly extends beyond a sidewall of the plurality of channel layers.

19. The method of claim 17 , further comprising:

replacing the dummy gate structure with an active gate structure.

20. The method of claim 17 , wherein the inner spacer comprises a plurality of portions, and each of the plurality of portions is vertically disposed between neighboring ones of the plurality of channel layers.