Semiconductor package, method of bonding workpieces and method of manufacturing semiconductor package
A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.
1. A semiconductor package, comprising:
a first semiconductor device comprising a first alignment pattern having a plurality of first scale patterns arranged in a first direction; and
a second semiconductor device mounted over the first semiconductor device and comprising a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns from a top view.
2. The semiconductor package as claimed in claim 1 , wherein the first semiconductor device comprises a first top metal layer having a first circuit pattern and the first alignment pattern insulated from the first circuit pattern.
3. The semiconductor package as claimed in claim 2 , wherein the second semiconductor device comprises a second top metal layer facing the first top metal layer and having a second circuit pattern electrically connected to the first circuit pattern and the second alignment pattern insulated from the second circuit pattern.
4. The semiconductor package as claimed in claim 1 , wherein a length of (n−1) scale pitches of the second scale pattern is equal to a length of (n) scale pitches of the first scale pattern.
5. The semiconductor package as claimed in claim 1 , wherein the plurality of first scale patterns are arranged in a zigzag manner deviated from the first direction, and the plurality of second scale patterns are arranged in a zigzag manner deviated from the second direction.
6. The semiconductor package as claimed in claim 1 , wherein a center of the plurality of first scale patterns is aligned with a center of the plurality of second scale patterns.
7. The semiconductor package as claimed in claim 1 , wherein the first alignment pattern further having a first alignment mark adjacent to the plurality of first scale patterns, and the second alignment pattern further having a second alignment mark adjacent to the plurality of second scale patterns.
8. The semiconductor package as claimed in claim 7 , wherein a contour of the first alignment mark is alignment with a contour of the second optical from a top view.
9. The semiconductor package as claimed in claim 1 , wherein the first semiconductor device comprises a plurality of first alignment marks arranged diagonally on the first semiconductor device, and the second semiconductor device comprises a plurality of second alignment marks arranged diagonally on the second semiconductor device.
10. A semiconductor package, comprising:
a first semiconductor device comprising a first alignment pattern having a plurality of first scale patterns separated from one another and arranged in a first direction; and
a second semiconductor device mounted over the first semiconductor device and comprising a second alignment pattern having a plurality of second scale patterns separated from one another and arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.
11. The semiconductor package as claimed in claim 10 , wherein a length of (n−1) scale pitches of the second scale pattern is equal to a length of (n) scale pitches of the first scale pattern.
12. The semiconductor package as claimed in claim 10 , wherein the plurality of first scale patterns are arranged in a zigzag manner deviated from the first direction, and the plurality of second scale patterns are arranged in a zigzag manner deviated from the second direction.
13. The semiconductor package as claimed in claim 10 , wherein a center of the plurality of first scale patterns is aligned with a center of the plurality of second scale patterns.
14. The semiconductor package as claimed in claim 10 , wherein the first alignment pattern further having a first alignment mark adjacent to the plurality of first scale patterns, and the second alignment pattern further having a second alignment mark adjacent to the plurality of second scale patterns.
15. The semiconductor package as claimed in claim 14 , wherein a contour of the first alignment mark is alignment with a contour of the second optical from a top view.
16. The semiconductor package as claimed in claim 10 , wherein the first semiconductor device comprises a plurality of first alignment marks arranged diagonally on the first semiconductor device, and the second semiconductor device comprises a plurality of second alignment marks arranged diagonally on the second semiconductor device.
17. A semiconductor package, comprising:
a first semiconductor device comprising a first alignment pattern having a plurality of first scale patterns arranged in a first direction; and
a second semiconductor device mounted over the first semiconductor device and comprising a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, wherein a length of (n−1) scale pitches of the second scale patterns is equal to a length of (n) scale pitches of the first scale patterns.
18. The semiconductor package as claimed in claim 17 , wherein the plurality of first scale patterns are arranged in a zigzag manner deviated from the first direction, and the plurality of second scale patterns are arranged in a zigzag manner deviated from the second direction.
19. The semiconductor package as claimed in claim 17 , wherein a center of the plurality of first scale patterns is aligned with a center of the plurality of second scale patterns.
20. The semiconductor package as claimed in claim 17 , wherein the first semiconductor device comprises a plurality of first alignment marks arranged diagonally on the first semiconductor device, and the second semiconductor device comprises a plurality of second alignment marks arranged diagonally on the second semiconductor device.