Three-dimensional memory devices
In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a plurality of channel structures each extending vertically through the memory stack, a conductive layer in contact with source ends of the plurality of channel structures, a first source contact electrically connected to the channel structures, and a second source contact electrically connected to the channel structures.
1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers;
a plurality of channel structures each extending vertically through the memory stack;
a conductive layer in contact with source ends of the plurality of channel structures;
a first type doped semiconductor layer between the memory stack and the conductive layer; and
a second type well in the first type doped semiconductor layer;
a first source contact electrically connected to the channel structures; and
a second source contact electrically connected to the channel structures.
2. The 3D memory device of claim 1 , wherein:
the first type is P-type; and
the second type is N-type.
3. The 3D memory device of claim 1 , wherein
the first source contact is in contact with the first type doped semiconductor layer; and
the second source contact is in contact with the second type well.
4. The 3D memory device of claim 1 , wherein the first type doped semiconductor layer comprises polysilicon.
5. The 3D memory device of claim 1 , wherein the conductive layer comprises a metal silicide layer and a metal layer.
6. The 3D memory device of claim 1 , wherein a thickness of the first type doped semiconductor layer is less than about 50 nm.
7. The 3D memory device of claim 1 , further comprising:
a peripheral circuit; and
a bonding interface between the peripheral circuit and the memory stack.
8. The 3D memory device of claim 7 , further comprising:
a first interconnect in contact with the first source contact;
a second interconnect in contact with the second source contact;
a first contact through the first type doped semiconductor layer, wherein the first type doped semiconductor layer is electrically connected to the peripheral circuit through at least the first source contact, the first interconnect, and the first contact; and
a second contact through the first type doped semiconductor layer, wherein the second type well is electrically connected to the peripheral circuit through at least the second source contact, the second interconnect, and the second contact.
9. The 3D memory device of claim 1 , further comprising:
a third contact through the first type doped semiconductor layer; and
a contact pad electrically connected to the third contact.
10. The 3D memory device of claim 1 , wherein each of the channel structures extends into the first type doped semiconductor layer.
11. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
a memory stack comprising interleaved conductive layers and dielectric layers,
a plurality of channel structures each extending vertically through the memory stack and electrically connected to the peripheral circuit,
a conductive layer comprising a metal silicide layer and a metal layer electrically connecting the plurality of channel structures,
a first type doped semiconductor layer between the memory stack and the conductive layer, and
a second type well in the first type doped semiconductor layer; and
a bonding interface between the first semiconductor structure and the second semiconductor structure.
12. The 3D memory device of claim 11 , wherein:
the first type is P-type; and
the second type is N-type.
13. The 3D memory device of claim 11 , wherein the second semiconductor structure further comprises:
a first source contact in contact with the first type doped semiconductor layer; and
a second source contact in contact with the N-well.
14. The 3D memory device of claim 13 , further comprising:
a first interconnect in contact with the first source contact;
a second interconnect in contact with the second source contact;
a first contact through the first type doped semiconductor layer, wherein the first type doped semiconductor layer is electrically connected to the peripheral circuit through at least the first source contact, the first interconnect, and the first contact; and
a second contact through the first type doped semiconductor layer, wherein the N-well is electrically connected to the peripheral circuit through at least the second source contact, the second interconnect, and the second contact.
15. The 3D memory device of claim 11 , wherein the first type doped semiconductor layer comprises polysilicon.
16. The 3D memory device of claim 11 , wherein a thickness of the first type doped semiconductor layer is less than about 50 nm.
17. The 3D memory device of claim 11 , further comprising:
a third contact through the first type doped semiconductor layer; and
a contact pad electrically connected to the third contact.
18. The 3D memory device of claim 11 , wherein each of the channel structures extends into the first type doped semiconductor layer.