Memory device containing constricted channel ends and methods of making the same
A memory die includes an alternating stack of insulating layers and electrically conductive layers, a dielectric spacer layer underlying the alternating stack, memory opening vertically extending through the alternating stack, and through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located under the dielectric spacer layer and contacting the pillar portion of the vertical semiconductor channel.
1 . A semiconductor structure that comprises a memory die, wherein the memory die comprises:
an alternating stack of insulating layers and electrically conductive layers;
a dielectric spacer layer underlying the alternating stack;
a memory opening vertically extending through the alternating stack, and through the dielectric spacer layer;
a memory opening fill structure located in the memory opening and comprising a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film; and
a source layer located under the dielectric spacer layer and contacting the pillar portion of the vertical semiconductor channel.
2 . The semiconductor structure of claim 1 , further comprising a tubular spacer that laterally surrounds the pillar portion, and is laterally spaced from the pillar portion by a cylindrical portion of the memory film.
3 . The semiconductor structure of claim 2 , wherein the tubular spacer comprises a semiconductor material or a conductive material.
4 . The semiconductor structure of claim 2 , wherein the tubular spacer comprises a dielectric oxide spacer.
5 . The semiconductor structure of claim 4 , further comprising a source-select-level conductive layer located between the alternating stack and the dielectric spacer layer, wherein:
the memory opening also vertically extends through the source-select-level conductive layer; and
the dielectric oxide spacer comprises a silicon oxide spacer.
6 . The semiconductor structure of claim 5 , wherein the silicon oxide spacer is interposed between a bottom portion of the memory opening fill structure and the source-select-level conductive layer and has a shape of a tapered pipe.
7 . The semiconductor structure of claim 6 , wherein the source-select-level conductive layer comprises an upper portion that overlies the silicon oxide spacer and a lower portion that laterally surrounds the silicon oxide spacer.
8 . The semiconductor structure of claim 5 , wherein a horizontal cross-sectional area of a volume that is enclosed by an inner tapered lateral surface of the silicon oxide spacer increases with a vertical distance from the source layer.
9 . The semiconductor structure of claim 5 , wherein a portion of the dielectric core that is located between a first horizontal plane including a bottom surface of the source-select-level conductive layer and a second horizontal plane including a top surface of the source-select-level conductive layer has a shape of an inverted circular cone.
10 . The semiconductor structure of claim 5 , wherein an interface between the source layer and the vertical semiconductor channel is located between a first horizontal plane including a bottom surface of the source-select-level conductive layer and a second horizontal plane including a top surface of the source-select-level conductive layer.
11 . The semiconductor structure of claim 10 , wherein:
the source layer comprises a metallic source layer having a pillar portion that vertically extends through the dielectric spacer layer; and
the pillar portion comprises a neck located about the first horizontal plane and having a minimum lateral dimension within the pillar portion.
12 . The semiconductor structure of claim 11 , wherein the metallic source layer comprises:
a metallic barrier liner comprising a metallic nitride material; and
a metal layer comprising a metal having a higher electrical conductivity than the metallic nitride material, wherein:
the metallic barrier liner contacts a bottom end of an inner sidewall of the memory film; and
the metal layer is located entirely below the first horizontal plane including a planar bottom surface of the source-select-level conductive layer.
13 . The semiconductor structure of claim 5 , wherein the electrically conductive layers and the source-select-level conductive layer comprise a same set of at least one conductive material.
14 . The semiconductor structure of claim 1 , further comprising a logic die bonded to the memory die.
15 . A method of forming a semiconductor structure, comprising:
forming a dielectric spacer layer, a semiconductor material layer, and an alternating stack of insulating layers and sacrificial material layers over a carrier substrate;
forming a memory opening through the alternating stack, the semiconductor material layer, and the dielectric spacer layer;
forming a dielectric oxide spacer by converting a surface portion of the semiconductor material layer into a dielectric oxide of a semiconductor material;
forming a memory opening fill structure in a remaining volume of the memory opening, wherein the memory opening fill structure comprises a memory film, a vertical semiconductor channel, and a dielectric core;
replacing the sacrificial material layers and the semiconductor material layer with electrically conductive layers and a source-select-level conductive layer, respectively;
removing the carrier substrate; and
forming a source layer such that a bottom end portion of the memory opening fill structure is replaced with a pillar portion of the source layer.
16 . The method of claim 15 , wherein:
the source layer comprises a metallic source layer; and
the metallic source layer is formed directly on an inner sidewall of the memory film and directly on a bottom end surface of the vertical semiconductor channel.
17 . The method of claim 16 , further comprising:
forming a source-side recess cavity by removing the bottom end portion of the memory opening fill structure, wherein a bottom surface of a remaining portion of the vertical semiconductor channel is exposed to the source-side recess cavity; and
depositing at least one metallic material in the source-side recess cavity and on a physically exposed planar surface of the dielectric spacer layer and on the remaining portion of the vertical semiconductor channel to form the metallic source layer.
18 . The method of claim 17 , wherein:
the source-side recess cavity has a neck at which a lateral dimension of the source-side recess cavity is at a minimum;
the neck is formed at or in proximity to a horizontal plane including a planar surface of the dielectric spacer layer that is proximal to the source-select-level conductive layer; and
an interface between the metallic source layer and the remaining portion of the vertical semiconductor channel is formed between a first horizontal plane containing a first horizontal surface of the source-select-level conductive layer and a second horizontal plane containing a second horizontal surface of the source-select-level conductive layer.
19 . The method of claim 15 , wherein:
the semiconductor material layer has a funnel-shaped sidewall that is exposed to the memory opening upon formation of the memory opening; and
the dielectric oxide spacer comprises a silicon oxide spacer having a shape of a tapered pipe which is oriented such that a horizontal cross-sectional area of a volume that is enclosed by a tapered inner sidewall of the silicon oxide spacer increases with a vertical distance from the carrier substrate.
20 . The method of claim 19 , wherein:
a volume of the memory opening that is laterally surrounded by the silicon oxide spacer has a neck at or about a horizontal plane including a top surface of the dielectric spacer layer;
the neck is completely filled by the vertical semiconductor channel upon formation of the vertical semiconductor channel;
an encapsulated cavity that is encapsulated by the vertical semiconductor channel is formed at a bottom portion of the memory opening underneath the horizontal plane including the top surface of the dielectric spacer layer; and
a bottom portion of the dielectric core that is formed below a horizontal plane including a top surface of the semiconductor material layer has a shape of an inverted circular cone having an apex above a horizontal plane including a bottom surface of the semiconductor material layer.