Three-dimensional memory device including trench-isolated memory planes and method of making the same
A three-dimensional memory device includes a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, and first bit lines electrically connected first vertical semiconductor channels, and a second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines and second bit lines electrically connected to second vertical channels. An inter-array backside trench laterally extend between the first three-dimensional memory plane and the second three-dimensional memory plane, and filled with an inter-array backside insulating material portion that provides electrical isolation between the three-dimensional memory planes.
1. A three-dimensional memory device, comprising:
a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, first memory openings vertically extending through a respective one of the first alternating stacks and filled with first memory opening fill structures including a respective first vertical semiconductor channel and first memory film, and first bit lines overlying the first alternating stacks, extending in a bit line direction over an area of the first alternating stacks, and electrically connected to a respective subset of the first vertical semiconductor channels;
a second three-dimensional memory plane spaced from the first three-dimensional memory plane along the bit line direction, the second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines, second memory openings vertically extending through a respective one of the second alternating stacks and filled with second memory opening fill structures including a respective second vertical semiconductor channel and second memory film, and second bit lines overlying the second alternating stacks, extending in the bit line direction over the area of the second alternating stacks and electrically connected to a respective subset of the second vertical semiconductor channels and electrically isolated from each of the first vertical semiconductor channels and the first bit lines;
an inter-array backside trench laterally extending along a word line direction which is perpendicular to the bit line direction between the first three-dimensional memory plane and the second three-dimensional memory plane and filled with an inter-array backside trench fill structure comprising an inter-array backside insulating material portion; and
a cut region extending along the word line direction and located over the inter-array backside trench at the level of the first bit lines and the second bit lines such that the first bit lines and the second bit lines do not cross over the cut region which comprises a boundary between the first and the second three-dimensional memory planes.
2. The three-dimensional memory device of claim 1 , wherein:
the first bit lines do not have any areal overlap with the area of the second alternating stacks in a plan view; and
the second bit lines do not have any areal overlap with the area of the first alternating stacks in the plan view.
3. The three-dimensional memory device of claim 1 , wherein the first bit lines and the second bit lines do not have any areal overlap with an area of the inter-array backside trench in a plan view.
4. The three-dimensional memory device of claim 1 , wherein:
the first alternating stacks comprise first memory blocks which are laterally spaced from each other by first backside trenches laterally extending along the word line direction and filled with first backside trench fill structures; and
the second alternating stacks comprise second memory blocks which are laterally spaced from each other by second backside trenches laterally extending along the word line direction and filled with second backside trench fill structures.
5. The three-dimensional memory device of claim 4 , wherein each of the first backside trench fill structures and the second backside trench fill structures comprises a respective backside insulating material portion having a same material composition as the inter-array backside insulating material portion.
6. The three-dimensional memory device of claim 5 , wherein:
each of the backside insulating material portions comprises a respective backside insulating spacer; and
the inter-array backside insulating material portion comprises an inter-array backside insulating spacer.
7. The three-dimensional memory device of claim 6 , wherein sidewalls of the backside insulating spacers have a same lateral thickness as a sidewall of the inter-array backside insulating spacer.
8. The three-dimensional memory device of claim 5 , wherein:
each of the first backside trench fill structures and the second backside trench fill structures comprises a respective conductive via structure; and
the inter-array backside trench fill structure comprises an inter-array conductive via structure having a same material composition as the conductive via structures of the first backside trench fill structures and the second backside trench fill structures.
9. The three-dimensional memory device of claim 1 , further comprising a peripheral circuit comprising:
a first bit line driver circuit electrically connected to the first bit lines; and
a second bit line driver circuit electrically connected to the second bit lines.
10. The three-dimensional memory device of claim 1 , wherein:
the first three-dimensional memory plane and the second three-dimensional memory plane are located within a memory die comprising memory-side bonding pads;
a peripheral circuit is located within a logic die comprising logic-side bonding pads which are bonded to a respective one of the memory-side bonding pads; and
the logic die overlies the topmost surfaces of the first alternating stacks and the second alternating stacks.
11. The three-dimensional memory device of claim 10 , wherein:
the peripheral circuit is located between a substrate of the logic die and a combination of the first three-dimensional memory plane and the second three-dimensional memory plane;
the three-dimensional memory device comprises metal interconnect structures embedded within dielectric material layers and providing electrical connection between the peripheral circuit and the first bit lines, the second bit lines, the first word lines, and the second word lines; and
the substrate of the logic die is more distal from a horizontal plane including a bonding interface between the memory die and the logic die than the peripheral circuit is from the horizontal plane.
12. The three-dimensional memory device of claim 10 , wherein the peripheral circuit comprises:
a first word line driver circuit electrically connected to the first word lines of the first three-dimensional memory plane and electrically isolated from the second three-dimensional memory plane; and
a second word line driver circuit electrically connected to the second word lines of the second three-dimensional memory plane and electrically isolated from the first three-dimensional memory plane.
13. The three-dimensional memory device of claim 1 , further comprising:
a first semiconductor material layer electrically connected to end portions of the first vertical semiconductor channels, underlying the first alternating stacks, and having an areal overlap with the first alternating stacks in a plan view along a vertical direction and not having any areal overlap with the second alternating stacks in the plan view; and
a second semiconductor material layer electrically connected to end portions of the second vertical semiconductor channels, underlying the second alternating stacks, and having an areal overlap with the second alternating stacks in the plan view and not having any areal overlap with the first alternating stacks in the plan view,
wherein the second semiconductor material layer and the first semiconductor material layer are discrete semiconductor material layers that are not in direct contact with each other, are laterally spaced apart from each other by a gap in which a bottom surface of the inter-array backside trench fill structure is exposed, and are electrically isolated from each other, wherein the gap laterally extends along the word line direction.
14. The three-dimensional memory device of claim 13 , wherein:
the first semiconductor material layer comprises a first source line located in the first three-dimensional memory plane and contacting each of the first memory opening fill structures and not contacting any of the second memory opening fill structures; and
the second semiconductor material layer comprises a second source line located in the second three-dimensional memory plane, contacting each of the second memory opening fill structures and not contacting the first substrate portion or any of the first memory opening fill structures.
15. The three-dimensional memory device of claim 13 , wherein a width of the gap between the first semiconductor material layer and the second semiconductor material layer is not less than a lateral distance between the first three-dimensional memory plane and the second three-dimensional memory plane.
16. The three-dimensional memory device of claim 13 , wherein a surface of the inter-array backside trench fill structure is physically exposed in the gap between the first three-dimensional memory plane and the second three-dimensional memory plane.
17. The three-dimensional memory device of claim 13 , wherein the inter-array backside trench fill structure does not have any areal overlap with any portion of the first semiconductor material layer in the plan view, and does not have any areal overlap with any portion of the second semiconductor material layer in the plan view.
18. The three-dimensional memory device of claim 1 , wherein:
the first alternating stacks within the first three-dimensional memory plane are laterally spaced apart from each other by first backside trench fill structures that laterally extend along the word line direction in the first three-dimensional memory plane;
the second alternating stacks within the second three-dimensional memory plane are laterally spaced apart from each other by second backside trench fill structures that laterally extend along the word line direction in the second three-dimensional plane and comprising a same set of at least one material as the first backside trench fill structures; and
the inter-array backside trench fill structure laterally extends along the word line direction and comprises the same set of at least one material as the first backside trench fill structures.
19. The three-dimensional memory device of claim 18 , wherein the inter-array backside trench fill structure further comprises a conductive via structure that is laterally surrounded by the inter-array backside insulating material portion, and is electrically isolated from the first alternating stacks, the second alternating stacks, the first semiconductor material layers, and the second semiconductor material layers.
20. The three-dimensional memory device of claim 1 , wherein the first bit lines are located entirely within an area of the first three-dimensional memory plane, and the second bit lines are located entirely within an area of the second three-dimensional memory plane.