Three-dimensional memory devices and manufacturing methods thereof and three-dimensional memories
The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, and a three-dimensional memory. The three-dimensional memory device includes a first memory cell and at least one second memory cell sequentially stacked on the first memory cell. Each memory cell includes a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, and the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and electrically connected with the CMOS device. The second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device facing away from the memory array device and electrically connected with the CMOS device. The memory array device of the first memory cell is bonded with the CMOS device of the adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly electrically connected with the second set of contacts of the adjacent second memory cell.
1 . A three-dimensional memory device, comprising at least two memory cells that are stacked sequentially, wherein the at least two memory cells include a first memory cell and at least one second memory cell stacked on the first memory cell, and a memory cell of the at least two memory cells comprises:
a memory array device;
a CMOS device stacked with and connected to the memory array device; and
a first set of contacts disposed on a side of the memory array device facing away from the CMOS device and connected with the CMOS device,
wherein the second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell and is connected with the CMOS device of the second memory cell,
wherein the memory array device of the first memory cell is bonded with the CMOS device of an adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly connected with the second set of contacts of the adjacent second memory cell,
wherein, when there is one second memory cell, the second memory cell is an outer second memory cell stacked on the first memory cell, and the first set of contacts of the outer second memory cell is used to connect to an external device, and
wherein, when there are multiple second memory cells, the multiple second memory cells are sequentially stacked on the first memory cell, and, for two adjacent ones of the second memory cells, the first set of contacts of a second memory cell close to the first memory cell is correspondingly connected with the second set of contacts of a second memory cell far away from the first memory cell, a second memory cell farthest away from the first memory cell along a stacking direction is defined as the outer second memory cell, and the first set of contacts of the outer second memory cell is used to connect to the external device.
2 . The three-dimensional memory device of claim 1 , further comprising an isolation layer and an array pad embedded in the isolation layer, wherein the isolation layer covers a side of the outer second memory cell facing away from the first memory cell and the first set of contacts of the outer second memory cell, and the array pad is correspondingly connected with the first set of contacts of the outer second memory cell and is used to connect to the external device.
3 . The three-dimensional memory device of claim 2 , further comprising a protective layer, wherein the protective layer covers a side of the isolation layer facing away from the outer second memory cell, and wherein the protective layer is provided with an opening in a position corresponding to the array pad, and the array pad is exposed through the opening to connect to the external device.
4 . The three-dimensional memory device of claim 1 , wherein the memory array device comprises an array substrate, and the first set of contacts of the memory cell of the at least two memory cells is disposed on a side of the array substrate of the memory array device facing away from the CMOS device, and
wherein the CMOS device comprises a CMOS substrate, and the second set of contacts of the second memory cell is disposed on a side of the CMOS substrate of the second memory cell facing away from the memory array device of the second memory cell.
5 . The three-dimensional memory device of claim 4 , wherein the memory cell of the at least two memory cells further comprises an interconnection channel that is disposed in the memory array device and the CMOS device of the memory cell where the interconnection channel is located, and
the interconnection channel is connected with the first set of contacts and the CMOS device of the memory cell where the interconnection channel is located, respectively, wherein the first set of contacts is connected to the CMOS device through the interconnection channel.
6 . The three-dimensional memory device of claim 5 , wherein the second memory cell further comprises conductive channels which penetrate through the CMOS substrate of the second memory cell and are connected with the second set of contacts and the CMOS device of the second memory cell respectively, wherein the second set of contacts is connected with the CMOS device of the second memory cell where the conductive channels are located through the conductive channels.
7 . The three-dimensional memory device of claim 1 , wherein the memory array device of the first memory cell and the memory array device of the second memory cell each include a preset number of layers of memory layers, and a value of the preset number of layers is an integer greater than 0 and less than 500.
8 . A three-dimensional memory, comprising:
a three-dimensional memory device comprising at least two memory cells that are stacked sequentially, wherein the at least two memory cells include a first memory cell and at least one second memory cell stacked on the first memory cell, and a memory cell of the at least two memory cells comprises:
a memory array device and a CMOS device that are stacked and electrically connected with each other; and
a first set of contacts disposed on a side of the memory array device facing away from the CMOS device and connected with the CMOS device,
wherein the second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device of the second memory cell facing away from the memory array device of the second memory cell and is connected with the CMOS device of the second memory cell,
wherein the memory array device of the first memory cell is bonded with the CMOS device of an adjacent second memory cell, and the first set of contacts of the first memory cell is correspondingly connected with the second set of contacts of the adjacent second memory cell,
wherein, when there is one second memory cell, the second memory cell is an outer second memory cell stacked on the first memory cell, and the first set of contacts of the outer second memory cell is used to connect to an external device, and
wherein, when there are multiple second memory cells, the multiple second memory cells are sequentially stacked on the first memory cell, and, for two adjacent ones of the second memory cells, the first set of contacts of a second memory cell close to the first memory cell is correspondingly connected with the second set of contacts of a second memory cell far away from the first memory cell, a second memory cell farthest away from the first memory cell along a stacking direction is defined as the outer second memory cell, and the first set of contacts of the outer second memory cell is used to connect to the external device.