Bonded semiconductor die assembly containing through-stack via structures and methods for making the same

1. A bonded assembly, comprising:

a first three-dimensional memory die comprising a first substrate including a first semiconductor material layer, first through-substrate connection structures vertically extending through the first semiconductor layer and having a respective vertical extent that is same as a thickness of the first semiconductor material layer, a first backside insulating layer contacting a backside of the first semiconductor material layer and embedding first substrate-side bonding pads that are electrically connected to a respective one of the first through-substrate connection structures, a first alternating stack of first insulating layers and first electrically conductive layers, first memory structures located in the first alternating stack, and a first stepped dielectric material portion contacting stepped surfaces of the first alternating stack;

a second three-dimensional memory die bonded to the first three-dimensional memory die, wherein the second three-dimensional memory die comprises a second alternating stack of second insulating layers and second electrically conductive layers, second memory structures located in the second alternating stack, and a second stepped dielectric material portion contacting stepped surfaces of the second alternating stack; and

driver circuit devices;

wherein:

the first electrically conductive layers have different lateral extents along a first horizontal direction that decrease with a respective vertical distance from the driver circuit devices; and

the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

2. The bonded assembly of claim 1 , wherein the stepped surfaces of the second alternating stack are laterally offset along the first horizontal direction from the stepped surfaces of the first alternating stack.

3. The bonded assembly of claim 1 , wherein the first three-dimensional memory die further comprises:

memory openings vertically extending through each layer within the first alternating stack, wherein the first memory structures are located in the memory openings and comprise a respective vertical semiconductor channel and a respective memory film;

first layer contact via structures vertically extending through the first stepped dielectric material portion and contacting a respective one of the first electrically conductive layers; and

first laterally-isolated through-stack via structures vertically extending through a region of the first alternating stack in which each layer of the first alternating stack is present and electrically connected to a respective one of the first layer contact via structures.

4. The bonded assembly of claim 3 , further comprising a logic die bonded to the first three-dimensional memory die, wherein the driver circuit devices comprise complementary metal oxide semiconductor (CMOS) transistors located in the logic die.

5. The bonded assembly of claim 4 , wherein:

the first alternating stack is located on a front side of the first substrate;

each of the first laterally-isolated through-stack via structures is electrically connected to a respective one of the first substrate-side bonding pads through a respective one of the first through-substrate connection structures; and

each of the first laterally-isolated through-stack via structures is in direct contact with the respective one of the first through-substrate connection structures.

6. The bonded assembly of claim 5 , wherein:

the logic die further comprises logic-die bonding pads embedded in logic-die dielectric material layers and electrically connected to a respective node of the CMOS transistors; and

the first substrate-side bonding pads are bonded to the logic-die bonding pads, or are electrically connected to the logic-die bonding pads through electrically conductive paths located within an intervening die located between the logic die and the first three-dimensional memory die.

7. The bonded assembly of claim 1 , wherein the first three-dimensional memory die is located between the driver circuit devices and the second three-dimensional memory die.

8. The bonded assembly of claim 7 , wherein:

the first three-dimensional memory die comprises first dielectric material layers that embed first metal interconnect structures and first interconnect-side bonding pads that are more distal from the driver circuit devices than the first alternating stack is from the driver circuit devices; and

the second three-dimensional memory die comprises second dielectric material layers that embed second metal interconnect structures and second interconnect-side bonding pads that are more proximal to the driver circuit devices than the second alternating stack is to the driver circuit devices; and

the first interconnect-side bonding pads are bonded to the second interconnect-side bonding pads.

9. The bonded assembly of claim 8 , wherein:

the second three-dimensional memory die further comprises second layer contact via structures vertically extending through the second stepped dielectric material portion and contacting a respective one of the second electrically conductive layers; and

each of the second layer contact via structures is electrically connected to a respective one of the second interconnect-side bonding pads by a respective subset of the second metal interconnect structures.

10. The bonded assembly of claim 7 , further comprising a third three-dimensional memory die bonded to the second three-dimensional die.

11. The bonded assembly of claim 1 , wherein the second three-dimensional memory die is located between the driver circuit devices and the first three-dimensional memory die.

12. The bonded assembly of claim 11 , further comprising a third three-dimensional memory die bonded to the first three-dimensional die.

13. The bonded assembly of claim 12 , wherein the third three-dimensional memory die comprises:

a third alternating stack of third insulating layers and third electrically conductive layers, wherein the third electrically conductive layers have different lateral extents along the first horizontal direction that increase with a respective vertical distance from the driver circuit devices;

third memory structures located in the third alternating stack;

a third stepped dielectric material portion contacting stepped surfaces of the third alternating stack; and

third layer contact via structures contacting a respective one of the third electrically conductive layers.

14. The bonded assembly of claim 1 , further comprising a logic die that comprises a logic-side semiconductor material layer, driver circuit devices that comprise complementary metal oxide semiconductor (CMOS) transistors located on the logic-side semiconductor material layer, and logic-side dielectric material layers embedding logic-side metal interconnect structures and logic-side bonding pads.

15. The bonded assembly of claim 14 , wherein the second three-dimensional memory die further comprises a second substrate including a second semiconductor material layer, second through-substrate connection structures vertically extending through the second semiconductor layer and having a respective vertical extent that is same as a thickness of the second semiconductor material layer, a second backside insulating layer contacting a backside of the second semiconductor material layer and embedding second substrate-side bonding pads that are electrically connected to a respective one of the second through-substrate connection structures.

16. The bonded assembly of claim 15 , wherein the logic-side bonding pads are bonded to the second substrate-side bonding pads.

17. The bonded assembly of claim 16 , wherein each of the second through-substrate connection structures comprises:

a substrate insulating spacer in direct contact with a sidewall of the second semiconductor layer; and

a laterally-isolated through-substrate via structure comprising a conductive material and laterally surrounded by the substrate insulating layer and spaced from the second semiconductor layer by the substrate insulating spacer.

18. The bonded assembly of claim 1 , wherein each of the first through-substrate connection structures comprises:

a substrate insulating spacer in direct contact with a sidewall of the first semiconductor layer; and

a laterally-isolated through-substrate via structure comprising a conductive material and laterally surrounded by the substrate insulating layer and spaced from the first semiconductor layer by the substrate insulating spacer.

19. The bonded assembly of claim 1 , wherein:

the first three-dimensional memory die further comprises a first contact-level dielectric layer embedding drain contact via structures that contact a respective one of the first memory structures; and

each of the first through-dielectric via structures have a vertical extent that is the same as a sum of a thickness of the first stepped dielectric material portion and a thickness of the first contact-level dielectric layer.

20. The bonded assembly of claim 1 , wherein:

the first three-dimensional memory die further comprises first through-dielectric via structures vertically extending through the first stepped dielectric material portion and contacting a respective one of the first through-substrate connection via structures, first dielectric material layers embedding first metal interconnect structures which electrically contact the respective first through-dielectric via structures, and first interconnect-side bonding pads embedded within the first dielectric material layers and contacting a respective one of the first metal interconnect structures; and

the second three-dimensional memory die further comprises second through-dielectric via structures vertically extending through the second stepped dielectric material portion and contacting a respective one of the second through-substrate connection via structures, second dielectric material layers embedding second metal interconnect structures which electrically contact the respective second through-dielectric via structures, and second interconnect-side bonding pads embedded within the second dielectric material layers and contacting a respective one of the second metal interconnect structures.