Three-dimensional memory device including laterally separated source lines and method of making the same
A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.
1 . A memory device, comprising:
a first memory block comprising first word lines and a first source layer segment; and
a second memory block comprising second word lines and a second source layer segment which is electrically isolated from the first source layer segment,
wherein the first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block across a first word line bridge region located between the first memory block and the second memory block.
2 . The memory device of claim 1 , wherein:
the first memory block and the second memory block further comprise memory opening fill structures, each of which comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements;
and the first source layer segment is electrically isolated from the second source layer segment by a first source isolation dielectric structure.
3 . The memory device of claim 2 , further comprising a third memory block comprising third word lines and memory opening fill structures.
4 . The memory device of claim 3 , wherein:
the second word lines are electrically isolated from the third word lines by a backside trench fill structure located in a backside trench extending between the second and the third memory blocks; and
the second source layer segment is located in both the second and the third memory blocks.
5 . The memory device of claim 4 , further comprising word line switching devices and source line switch devices, wherein:
each one of the word line switching devices controls both a respective first word line and a respective second word line which is electrically connected to the respective first word line across the first word line bridge region;
the first source layer segment is controlled by a first one of the source line switch devices; and
the second source layer segment is controlled by a second one of the source line switch devices.
6 . The memory device of claim 3 , wherein:
the third memory block further comprises a third source layer segment which is electrically isolated from the second source layer segment by a second source isolation dielectric structure; and
the second word lines are electrically connected to the respective third word lines across a second word line bridge region located between the second memory block and the third memory block.
7 . The memory device of claim 6 , further comprising word line switching devices and source line switch devices, wherein:
each one of the word line switching devices controls a respective first word line, a respective second word line which is electrically connected to the respective first word line across the first word line bridge region, and a respective third word line which is electrically connected to the respective second word line across the second word line bridge region;
the first source layer segment is controlled by a first one of the source line switch devices;
the second source layer segment is controlled by a second one of the source line switch devices; and
the third source layer segment is controlled by a third one of the source line switch devices.
8 . The memory device of claim 1 , wherein:
the first memory block and the second memory block are located in a first unit structure which comprises one of multiple instances of the unit structures that laterally extend along a first horizontal direction and repeated along a second horizontal direction that is perpendicular to the first horizontal direction;
each instance of the unit structures comprises a respective alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction;
the respective alternating stack is laterally spaced from alternating stacks in neighboring instances of the unit structures by a respective backside trench that is filled with a respective backside trench fill structure; and
a laterally alternating sequence of source layer segments and source isolation dielectric structures located underneath the alternating stacks.
9 . The memory device of claim 8 , wherein each instance of the unit structures comprises:
first memory opening fill structures that vertically extend through the respective alternating stack on a first side of a respective underlying source isolation dielectric structure and that extend into a respective first source layer segment; and
second memory opening fill structures that vertically extend through the respective alternating stack on a second side of the respective underlying source isolation dielectric structure and extend into a respective second source layer segment that is laterally spaced from and is electrically isolated from the respective first source layer segment by the respective underlying source isolation dielectric structure.
10 . The memory device of claim 9 , wherein:
each of the first memory opening fill structures and the second memory opening fill structures comprise a respective vertical semiconductor channel and a respective vertical stack of memory elements;
each source isolation dielectric structure contacts and underlies a middle portion of a respective one of the alternating stacks and each source layer segment extends between a respective neighboring pair of source isolation dielectric structures; and
the source isolation dielectric structures laterally extend along the first horizontal direction.
11 . The memory device of claim 9 , wherein each of the source layer segments comprises:
a lower source-level material layer comprising a first doped semiconductor material;
an upper source-level material layer comprising a second doped semiconductor material; and
a source contact layer comprising a third doped semiconductor material and located between the upper source-level material layer and the lower source-level material layer.
12 . The memory device of claim 11 , wherein:
each of the backside trench fill structures comprises a backside contact via structure and a backside insulating spacer that laterally surrounds the backside contact via structure;
the backside contact via structure within each of the backside trench fill structures contacts a surface of a respective source contact layer;
each vertical semiconductor channel in the first memory opening fill structures contacts a source contact layer within the respective first source layer segment; and
each vertical semiconductor channel in the second memory opening fill structures contacts a source contact layer within the respective second source layer segment.
13 . The memory device of claim 9 , wherein the first and the second word lines laterally extend continuously between a respective neighboring pair of backside trench fill structures in the first unit structure.
14 . The memory device of claim 9 , further comprising:
a semiconductor substrate underlying the multiple instances of the unit structures; and
a peripheral circuitry located on the semiconductor substrate and electrically connected to the electrically conductive layers and the first and then second source layer segments through lower metal interconnect structures underlying the multiple instances of the unit structures, connection via structures located at a same level as the multiple instances of the unit structures, and upper metal interconnect structures overlying the multiple instances of the unit structures.
15 . The memory device of claim 9 , wherein the first unit structure further comprises a third memory block comprising:
third word lines which are electrically connected to the second word lines;
a third source layer segment which is electrically isolated from the second source layer segment by a second source isolation dielectric structure; and
third memory opening fill structures that vertically extend through the respective alternating stack on a second side of the second source isolation dielectric structure and that extend into the third source layer segment.
16 . The memory device of claim 15 , further comprising a backside trench fill structure contacting a first source isolation dielectric structure of the source isolation dielectric structures and contacting the alternating stacks in the first unit structure and another alternating stack located within a neighboring instance of the unit structures.
17 . The memory device of claim 16 , further comprising a logic die bonded to a memory die containing the unit structures.
18 . A method of forming a memory device, comprising:
forming a laterally alternating sequence of source layer segments and source isolation dielectric structures;
forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers;
forming memory openings through the vertically alternating sequence;
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel;
dividing the vertically alternating sequence into in-process alternating stacks of insulating layers and sacrificial material layers by forming backside trenches that laterally extend along a first horizontal direction and laterally spaced apart along a second horizontal direction;
replacing the sacrificial material layers with electrically conductive layers to form alternating stacks of insulating layers and electrically conductive which are laterally spaced apart from each other by the backside trenches and which extend over at least one of the source isolation dielectric structures; and
bonding a logic die to a memory die containing the memory opening fill structures, wherein at least three source layer segments are located between adjacent backside trenches.
19 . The method of claim 18 , wherein the backside trenches and the source layer segments are staggered along the second horizontal direction such that each backside trench is formed between a neighboring pair of source layer segments.