Three-dimensional memory device with source line isolation and method of making the same
A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.
1. A memory device, comprising:
a source layer comprising at least one doped semiconductor material;
alternating stacks of insulating layers and electrically conductive layers located over the source layer, extending along a first horizontal direction and laterally spaced apart from each other along the second horizontal direction by backside trenches, wherein the backside trenches comprise at least one first backside trench containing with a respective backside contact via structure comprising an electrically conductive material contacting the source layer, and at least one second backside trench containing a respective dielectric trench fill structure which extends from above the topmost surfaces of the alternating stacks to at least a bottom surface of the source layer;
memory openings, wherein each of the memory openings vertically extends through a respective one of the alternating stacks; and
memory opening fill structures located in the memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel.
2. The memory device of claim 1 , wherein the source layer comprises:
a lower source-level material layer comprising a first doped semiconductor material;
an upper source-level material layer comprising a second doped semiconductor material; and
a source contact layer comprising a third doped semiconductor material and located between the upper source-level material layer and the lower source-level material layer.
3. The memory device of claim 2 , wherein each of the respective backside contact via structures contacts a surface of the source contact layer.
4. The memory device of claim 2 , wherein the source contact layer contacts sidewalls of the vertical semiconductor channels.
5. The memory device of claim 4 , wherein the respective vertical stack of memory elements comprises a portion of a respective memory film that laterally surrounds the respective vertical semiconductor channel, has a respective annular concave bottom surface contacting the source contact layer, and has a respective cylindrical outer surface contacting the upper source-level material layer and each insulating layer within a respective one of the alternating stacks.
6. The memory device of claim 1 , wherein each of the backside contact via structures is laterally surrounded by and is laterally spaced from a respective neighboring pair of alternating stacks by a respective backside insulating spacer.
7. The memory device of claim 1 , further comprising a plurality contact-level dielectric layers, each overlying a respective one of the alternating stacks and a respective subset of the memory opening fill structures and having a respective top surface located within a horizontal plane including top surfaces of the backside contact via structures and the dielectric trench fill structures.
8. The memory device of claim 7 , wherein:
the at least one first backside trench contains a respective backside insulating spacer laterally surrounding the respective backside contact via structure; and
each of the plurality contact-level dielectric layers contacts:
sidewalls of a pair of backside insulating spacers; or
a sidewall of a respective backside insulating spacer and a sidewall of the dielectric trench fill structure.
9. The memory device of claim 7 , wherein:
each of the memory opening fill structures further comprises a respective drain region comprising a respective doped semiconductor material; and
each of the plurality contact-level dielectric layers overlies a horizontal plane including top surface of the drain regions.
10. The memory device of claim 1 , wherein dielectric trench fill structure comprises silicon oxycarbide or silicon carbonitride.
11. The memory device of claim 1 , wherein a contact area between the source layer and the dielectric trench fill structure vertically extends continuously from a top surface of the source layer to a bottom surface of the source layer.
12. The memory device of claim 1 , wherein:
the dielectric trench fill structure vertically extends from above the topmost surfaces of the alternating stacks to below the bottom surface of the source layer;
the dielectric trench fill structure separates the source layer into first and second source layer portions;
the first source layer portion contacts sidewalls of the vertical semiconductor channels of memory opening fill structures located in a first alternating stack of the alternating stacks;
the second source layer portion contacts sidewalls of the vertical semiconductor channels of memory opening fill structures located in a second alternating stack of the alternating stacks; and
the at least one second backside trench is completely filled with the respective dielectric trench fill structure.
13. The memory device of claim 1 , further comprising:
a semiconductor substrate underlying source layer; and
a peripheral circuitry located on the semiconductor substrate and electrically connected to the electrically conductive layers.
14. The memory device of claim 1 , wherein at least two of the first backside trenches containing the respective backside contact via structures are located between a nearest neighbor pair of the second backside trenches containing the respective dielectric trench fill structure.