Three-dimensional memory device including metal silicide source regions and methods for forming the same
A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.
1. A semiconductor structure comprising a memory die, the memory die comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack;
a memory opening fill structure located in the memory opening and comprising a memory film, a vertical semiconductor channel, a source region comprising a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region comprising a doped semiconductor material contacting a second end of the vertical semiconductor channel;
a source contact layer contacting the source region; and
a semiconductor material layer contacting a horizontal surface of one of the insulating layers;
wherein an interface between the source contact layer and the source region is located within a same horizontal plane as an interface between the source contact layer and the semiconductor material layer.
2. The semiconductor structure of claim 1 , further comprising a logic die bonded to the memory die, wherein the logic die comprises field effect transistors, logic-side metal interconnect structures, and a logic-side bonding pad that is bonded to the source contact layer side of the memory die.
3. The semiconductor structure of claim 2 , wherein:
the source contact layer comprises a memory-side copper-containing layer; and
the logic-side bonding pad comprises a logic-side copper containing layer that is bonded to the memory-side copper-containing layer by copper-to-copper bonding.
4. A semiconductor structure comprising a memory die, the memory die comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack;
a memory opening fill structure located in the memory opening and comprising a memory film, a vertical semiconductor channel, a source region comprising a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region comprising a doped semiconductor material contacting a second end of the vertical semiconductor channel; and
a source contact layer contacting the source region;
wherein the source contact layer contacts a sidewall and a bottom surface of the source region; and
wherein the source contact layer contacts a horizontal surface of one of the insulating layers.
5. The semiconductor structure of claim 4 , further comprising a logic die bonded to the memory die, wherein the logic die comprises field effect transistors, logic-side metal interconnect structures, and a logic-side bonding pad that is bonded to the source contact layer side of the memory die.
6. The semiconductor structure of claim 5 , wherein:
the source contact layer comprises a memory-side copper-containing layer; and
the logic-side bonding pad comprises a logic-side copper containing layer that is bonded to the memory-side copper-containing layer by copper-to-copper bonding.