Gate structures for stacked semiconductor devices

1. A semiconductor device, comprising:

a first transistor device of a first type, comprising:

a first plurality of nanostructures;

a first pair of source/drain structures; and

a first gate structure on the first plurality of nanostructures;

a second transistor device of a second type formed over the first transistor device, the second transistor device comprising:

a second plurality of nanostructures over the first plurality of nanostructures;

a second pair of source/drain structures over the first pair of source/drain structures; and

a second gate structure on the second plurality of nanostructures and over the first plurality of nanostructures;

a first isolation structure in contact with the first and second pluralities of nanostructures; and

a second isolation structure in contact with a top surface of the first pair of source/drain structures.

2. The semiconductor device of claim 1 , wherein the first transistor device comprises a p-type field effect transistor (PFET) and the second transistor device comprises an n-type field effect transistor (NFET).

3. The semiconductor device of claim 1 , wherein the first transistor device comprises an n-type field effect transistor (NFET) and the second transistor device comprises a p-type field effect transistor (PFET).

4. The semiconductor device of claim 1 , further comprising a plurality of spacers, wherein a spacer of the plurality of spacers is formed between adjacent nanostructures of the first plurality of nanostructures.

5. The semiconductor device of claim 1 , further comprising a pair of spacers formed on sidewalk of the first isolation structure.

6. The semiconductor device of claim 5 , wherein the second isolation structure is in contact with a spacer of the pair of spacers.

7. The semiconductor device of claim 5 , wherein the pair of spacers is in contact with the first and second pluralities of nanostructures.

8. The semiconductor device of claim 1 , wherein a width of the first isolation structure is less than a width of a nanostructure of the first plurality of nanostructures.

9. The semiconductor device of claim 1 , wherein the first isolation structure is in contact with a topmost nanostructure of the first plurality of nanostructures and a bottommost nanostructure of the second plurality of nanostructures.

10. The semiconductor device of claim 1 , wherein the second isolation structure is in contact with a bottom surface of the second pair of source/drain structures.

11. A semiconductor structure, comprising:

a first transistor device, comprising:

a first plurality of nanostructures;

a first gate dielectric layer wrapping around each nanostructure of the first plurality of nanostructures;

a first work function layer on the first gate dielectric layer;

a first gate electrode on the first work function layer; and

a first source/drain region in contact with the first plurality of nanostructures;

a second transistor device, comprising:

a second plurality of nanostructures;

a second gate dielectric layer;

a second work function layer on the second gate dielectric layer;

a second gate electrode on the second work function layer; and

a second source/drain region in contact with the second plurality of nanostructures; and

a gate isolation structure between the first and second pluralities of nanostructures, wherein the gate isolation structure is in contact with a topmost nanostructure of the first plurality of nanostructures and a bottommost nanostructure of the second plurality of nanostructures.

12. The semiconductor structure of claim 11 , wherein the first transistor device comprises a p-type field effect transistor (PFET) and the second transistor device comprises an n-type field effect transistor (NFET).

13. The semiconductor structure of claim 11 , wherein the first transistor device comprises an n-type field effect transistor (NFET) and the second transistor device comprises a p-type field effect transistor (PFET).

14. The semiconductor structure of claim 11 , further comprising a source/drain isolation structure between the first and second source/drain regions.

15. The semiconductor structure of claim 14 , further comprising a pair of spacers formed on sidewalls of the gate isolation structure, wherein the source/drain isolation structure is in contact with a spacer of the pair of spacers.

16. A method, comprising:

forming a first plurality of semiconductor layers on a substrate;

forming a first isolation layer on the first plurality of semiconductor layers;

forming a second plurality of semiconductor layers on the first isolation layer;

removing portions of the first plurality of semiconductor layers to form a first plurality of nanostructures;

forming a first gate structure on the first plurality of nanostructures;

removing the first isolation layer;

removing portions of the second plurality of semiconductor layers to form a second plurality of nanostructures;

depositing a second isolation layer between the first and second pluralities of nanostructures; and

forming a second gate structure on the second plurality of nanostructures.

17. The method of claim 16 , wherein forming the first isolation layer comprises depositing silicon carbide.

18. The method of claim 16 , wherein forming the first isolation layer comprises depositing a silicon germanium material, and wherein a germanium atomic concentration of the silicon germanium material is between about 15% and about 25%.

19. The method of claim 16 , wherein forming the first isolation layer comprises depositing a compound comprising silicon, germanium, and tin.

20. The method of claim 16 , wherein removing the first isolation layer and removing the portions of the second plurality of semiconductor layers are performed during a same etching process.