Isolation between vertically stacked nanosheet devices
View Patent ↗A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.
1. A semiconductor structure comprising:
a bottom nanosheet device comprising a series of bottom channels arranged vertically and surrounded by a bottom work function metal;
a top nanosheet device comprising a series of top channels arranged vertically and surrounded by a top work function metal, the top nanosheet device vertically aligned with and stacked on top of the bottom nanosheet device;
two or more partial insulating layers disposed between the bottom nanosheet device and the top nanosheet device, the two or more partial insulating layers each separated vertically from one another by a series of inner spacers, and each of the two or more partial insulating layers comprises a thickness less than a thickness of any one channel from either the series of bottom channels or the series of top channels;
the bottom work function metal horizontally separating two portions of a first partial insulating layer of the two or more partial insulating layers; and
the top work function metal horizontally separating two portions of a second partial insulating layer of the two or more partial insulating layers.
2. The semiconductor structure according to claim 1 , wherein
the series of inner spacers is further disposed along vertical side surfaces of the bottom work function metal, and further arranged between and separating each of the bottom channels; and
the series of inner spacers is further arranged between and separating each of the top channels, and further disposed along vertical side surfaces of the top work function metal, wherein first vertical side surfaces of the series of inner spacers are vertically aligned with first vertical side surfaces of the two or more partial insulating layers.
3. The semiconductor structure according to claim 1 , wherein
each of the two portions of the first partial insulating layer comprises a width greater than a width of each inner spacer of the series of inner spacers.
4. The semiconductor structure according to claim 1 , wherein
the bottom work function metal and the top work function metal comprise the same material.
5. The semiconductor structure according to claim 1 , wherein
the bottom work function metal and the top work function metal comprise different materials.
6. The semiconductor structure according to claim 1 , further comprising:
a top source drain region in direct contact with ends of each top channel in the series of top channels; and
a bottom source drain region in direct contact with ends of each bottom channel in the series of bottom channels.
7. A semiconductor structure comprising:
a top nanosheet device comprising a series of top channels and a top work function metal stacked on top of and vertically aligned with a bottom nanosheet device comprising a series of bottom channels and a bottom work function metal;
an intermediate region disposed between the top nanosheet device and the bottom nanosheet device, wherein the intermediate region comprises a series of inner spacers each vertically separated from one another by a partial insulating layer of a plurality of partial insulating layers, wherein the bottom work function metal and the top work function metal together horizontally separates two portions of each of the plurality of partial insulating layers, and wherein the plurality of partial insulating layers have a thickness that is less than a thickness of any one channel from the top nanosheet device or the bottom nanosheet device.
8. The semiconductor structure according to claim 7 , wherein
the series of bottom channels are arranged vertically and surrounded by the bottom work function metal, and
the series of top channels are arranged vertically and surrounded by the top work function metal.
9. The semiconductor structure according to claim 8 , wherein
the series of inner spacers is further arranged between and separating each of the bottom channels, along vertical side surfaces of the bottom work function metal; and
the series of inner spacers is further arranged between and separating each of the top channels, along vertical side surfaces of the top work function metal.
10. The semiconductor structure according to claim 7 , wherein
first vertical side surfaces of the series of inner spacers are vertically aligned with first vertical side surfaces of the partial insulating layers.
11. The semiconductor structure according to claim 7 , wherein
each of the partial insulating layers comprises a width greater than a width of each spacer of the series of inner spacers.
12. A semiconductor structure comprising:
a bottom nanosheet device comprising a series of bottom channels arranged vertically and surrounded by a bottom work function metal;
a top nanosheet device comprising a series of top channels arranged vertically and surrounded by a top work function metal, the top nanosheet device vertically aligned with and stacked on top of the bottom nanosheet device; and
a bottom intermediate region disposed between the top nanosheet device and the bottom nanosheet device and a top intermediate region disposed between the top nanosheet device and the bottom intermediate region, wherein the bottom intermediate region comprises a first series of inner spacers each vertically separated from one another by a bottom partial insulating layer of a plurality of bottom partial insulating layers, wherein the bottom work function metal horizontally separates two portions of each of the plurality of bottom partial insulating layers, and wherein the plurality of bottom partial insulating layers comprise a thickness that is less than a thickness of any one channel from either the series of bottom channels or the series of top channels.
13. The semiconductor structure according to claim 12 , further comprising:
wherein the top intermediate region comprises a second series of inner spacers each vertically separated from one another by a top partial insulating layer, wherein the top work function metal horizontally separates two portions of each top partial insulating layer.
14. The semiconductor structure according to claim 12 , further comprising:
a third series of inner spacers being arranged between and separating each of the bottom channels and along vertical side surfaces of the bottom work function metal;
a fourth series of inner spacers being arranged between and separating each of the top channels and along vertical side surfaces of the top work function metal, and
wherein first vertical side surfaces of the third series of inner spacers and the fourth series of inner spacers are vertically aligned with first vertical side surfaces of the bottom partial insulating layers of the bottom intermediate region.
15. The semiconductor structure according to claim 12 , wherein
each of the bottom partial insulating layers comprises a width greater than a width of the first series of inner spacers.
16. The semiconductor structure according to claim 12 , further comprising:
a top source drain region in direct contact with ends of each top channel of the series of top channels; and
a bottom source drain region in direct contact with ends of each bottom channel of the series of bottom channels.
17. The semiconductor structure according to claim 12 , wherein
the bottom work function metal and the top work function metal comprise different materials.