IP Library Patent Application 17462990
Patent Application
App. No. 17/462,990

WAFER CARRIER ASSEMBLY WITH PEDESTAL AND COVER RESTRAINT ARRANGEMENTS THAT CONTROL THERMAL GAPS

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Quick Facts
Patent No.
US None
App. No.
17/462,990
Abstract

A wafer carrier assembly as described herein improves thermal control across a top surface thereof to maintain highly controlled deposition locations and thicknesses.

Claims (12)

1 . A wafer carrier assembly for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), the wafer carrier assembly comprising:

a base including a generally planar bottom surface and a top surface that is generally parallel to the bottom surface, wherein the top surface further includes a plurality of pedestals and a plurality of platforms extending above the top surface; and

a thermal cover defining a plurality of pockets, wherein the thermal cover is configured to be coupled to the base by at least one fastener and the plurality of pockets are arranged such that each pocket of the plurality of pockets is aligned with a corresponding platform of the plurality of platforms when the thermal cover is supported by the plurality of pedestals of the base, the thermal cover further defining an edge portion having a reduced thickness proximate each of the plurality of pockets on which the wafer for that pocket is carried;

wherein the pedestals and the platforms of the wafer carrier and the edge portion of the thermal cover are sized such that a set of thermal control gaps are defined that maintain a desired thermal profile along the top surface of the wafer carrier assembly.

2 . The wafer carrier assembly of claim 1 , wherein a wafer positioned in a pocket of the plurality of pockets is arranged above the corresponding platform of the pocket at a distance that is less than a height of the pedestals relative to the top surface.

3 . The wafer carrier assembly of claim 1 , wherein the edge portion of the thermal cover is shaped to have a rectangular cutout portion.

4 . The wafer carrier assembly of claim 1 , wherein the pedestals are the only physical connection between the thermal cover and the substrate.

5 . The wafer carrier assembly of claim 1 , wherein the thermal cover includes a radially outer edge portion that extends away from the base.

6 . The wafer carrier assembly of claim 1 , wherein the base includes a radially outer edge portion that extends from the top surface.

7 . The wafer carrier assembly of claim 1 , further comprising a plurality of pins configured to couple the base and the thermal cover.

8 . The wafer carrier assembly of claim 7 , wherein the plurality of pins are inserted at an angle relative to the top surface of the wafer carrier assembly.

9 . The wafer carrier assembly of claim 1 , wherein the desired thermal profile is uniform.

Assignments (3)
SECURITY INTEREST Recorded Jun 16, 2025
From: VEECO INSTRUMENTS INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 071649/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2022
From: KRISHNAN, SANDEEP; MITROVIC, BOJAN; ARMOUR, ERIC A.; RASHKOVSKY, YULIY; MAXWELL, ROBERT S., IV; VAN DOREN, MATTHEW J.
To: VEECO INSTRUMENTS INC.
Reel/Frame 061660/0494 →
PATENT SECURITY AGREEMENT Recorded Dec 16, 2021
From: VEECO INSTRUMENTS INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 058533/0321 →