Semiconductor device

1. A semiconductor device comprising:

a first semiconductor chip having a first transistor region and a non-transistor region; and

a plurality of through vias formed in the non-transistor region,

wherein the plurality of through vias include:

an active via electrically connected to a circuit; and

a floating via having a floating potential,

wherein the non-transistor region is arranged between the first transistor region and a second transistor region in a plan view, and

wherein the plurality of through vias arranged at a closest place to a first boundary line between the second transistor region and the non-transistor region in a plan view are a plurality of active vias composed of the active via electrically connected to a protection circuit.

2. The semiconductor device according to claim 1 ,

wherein at least a part of the through vias arranged at a closest place to a second boundary line between the first transistor region and the non-transistor region in a plan view is the floating via.

3. The semiconductor device according to claim 1 ,

wherein arrangement density of a diffusion layer formed in the first transistor region is higher than arrangement density of a diffusion layer formed in the non-transistor region.

4. The semiconductor device according to claim 1 ,

wherein no through via is formed in the first transistor region.

5. The semiconductor device according to claim 1 , further comprising a second semiconductor chip laminated on the first semiconductor chip,

wherein the active via is electrically connected to the second semiconductor chip.

6. The semiconductor device according to claim 5 ,

wherein the active via functions as a supply path for power supplied to a circuit formed on the second semiconductor chip.

7. The semiconductor device according to claim 6 ,

wherein a protection circuit configured to suppress destruction of the active via due to plasma charge-up is not formed on the first semiconductor chip.

8. The semiconductor device according to claim 1 ,

wherein the floating via has a function of suppressing destruction of the active via due to plasma charge-up.

9. The semiconductor device according to claim 1 ,

wherein the floating via is arranged at a place where destruction due to plasma charge-up more easily occurs than that of the active via.

10. The semiconductor device according to claim 2 ,

wherein the second boundary line includes a convex portion protruding from the non-transistor region toward the first transistor region in a plan view, and

wherein the floating via is formed in the convex portion.

11. The semiconductor device according to claim 1 , further comprising a laminated structure in which a plurality of semiconductor chips are laminated,

wherein the first semiconductor chip is a semiconductor device which is a semiconductor chip arranged in a lowermost layer among the plurality of semiconductor chips constituting the laminated structure.