IP Library Granted Patent US 12,463,154
Granted Patent B2
US 12,463,154 · App. 18/758,688 · Granted Nov 4, 2025

Semiconductor device

Inventor: Yoshihiro Ohara (Tokyo, JP)
Assignee: Renesas Electronics Corporation
H01L23/60H01L23/481H01L23/5286H01L25/0652H01L2225/06513H01L2225/06544H01L2225/06586
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,463,154
App. No.
18/758,688
Granted
Nov 4, 2025
Kind
B2
Abstract

A part among a plurality of through vias formed in a non-transistor region is a floating via having a floating potential.

Claims (9)

1 . A semiconductor device comprising:

a semiconductor chip having a transistor region and a non-transistor region; and

a plurality of through vias formed in the non-transistor region,

wherein the plurality of through vias include:

an active via electrically connected to a circuit;

a floating via having a floating potential, the floating via being disposed between the active via and a boundary between the transistor region and the non-transistor region in a plan view, the floating via being configured to undergo dielectric breakdown during plasma charge-up to become electrically connected to a back surface wiring to which a ground potential is supplied, thereby protect the active via from plasma-induced damage; and

a damage via having a ground potential, the damage via being disposed between the active via and the boundary between the transistor region and the non-transistor region in a plan view, the damage via being formed by the floating via becoming electrically connected to the back surface wiring to which the ground potential is supplied due to the dielectric breakdown occurring in the floating via.

2 . The semiconductor device according to claim 1 ,

wherein the damage via is formed on a back surface of the semiconductor chip and is connected to the back surface wiring to which the ground potential is supplied.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2024
From: OHARA, YOSHIHIRO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 067875/0916 →
Priority Claims (1)
JP 2020-152505 · Sep 11, 2020 · national
Continuity (2)
Division 17467964 · Sep 7, 2021
Related Publication 20240363557A1 · Oct 31, 2024
References Cited (35)
US 8174124B2 · Chiu · 2012 [cited by examiner]
US 11437708B2 · Huang · 2022 [cited by examiner]
US 11594471B2 · Son · 2023 [cited by examiner]
US 11632050B2 · Kansaku · 2023 [cited by examiner]
US 11769746B2 · Jang · 2023 [cited by examiner]
US 11823982B2 · Son · 2023 [cited by examiner]
US 11855021B2 · Lin · 2023 [cited by examiner]
US 12009308B2 · Son · 2024 [cited by examiner]
US 12062627B2 · Ohara · 2024 [cited by examiner]
US 20070134819A1 · Uchiyama · 2007 [cited by examiner]
US 20100171226A1 · West · 2010 [cited by examiner]
US 20110248404A1 · Chiu · 2011 [cited by examiner]
US 20130313690A1 · Miyazaki · 2013 [cited by examiner]
US 20160225679A1 · Kannan · 2016 [cited by examiner]
US 20170221877A1 · Lai · 2017 [cited by examiner]
US 20210305678A1 · Huang · 2021 [cited by examiner]
US 20220084960A1 · Ohara · 2022 [cited by examiner]
US 20220368004A1 · Huang · 2022 [cited by examiner]
US 20240363557A1 · Ohara · 2024 [cited by examiner]
CN 113178433A · 2021 [cited by examiner]
CN 114171454A · 2022 [cited by examiner]
DE 102021101251A1 · 2021 [cited by examiner]
EP 3968370A1 · 2022 [cited by examiner]
JP 2013247273A · 2013 [cited by applicant]
JP 2015088508A · 2015 [cited by examiner]
JP 2022046884A · 2022 [cited by examiner]
JP 7434118B2 · 2024 [cited by examiner]
JP 2024050842A · 2024 [cited by examiner]
KR 102494655B1 · 2023 [cited by examiner]
KR 20230017602A · 2023 [cited by examiner]
Extended European Search Report issued in corresponding European Patent Application No. 21195400.3-1211, dated Feb. 10, 2022. [cited by applicant]
Y. Fukumoto et al., “Development of Plasma Charge-up Damage Evaluation Wafers”, R&D Kobe Steel Engineering Reports, vol. 52, No. 2, Sep. 2002. [cited by applicant]
Non-Final Rejection issued in U.S. Appl. No. 17/467,964, dated Dec. 7, 2023. [cited by applicant]
Notice of Allowance issued in U.S. Appl. No. 17/467,964, dated Apr. 2, 2024. [cited by applicant]
Notice of Reasons for Refusal received in Japanese Patent Application No. 2020-152505, mailed Oct. 24, 2023. [cited by applicant]