Semiconductor package

1. A semiconductor package, comprising:

a substrate;

through-electrodes penetrating the substrate;

first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively;

at least one second bump disposed between the first bumps, the at least one second bump being electrically floated; and

an underfill covering the substrate, the first bumps, and the at least one second bump,

wherein the first bumps and the at least one second bump constitute one row in the first direction, and

wherein the at least one second bump is disposed at a higher level from the substrate than the first bumps.

2. The semiconductor package as claimed in claim 1 , further comprising:

an insulating pattern disposed between the substrate and the at least one second bump.

3. The semiconductor package as claimed in claim 2 , wherein the insulating pattern has through-holes overlapping top surfaces of the through-electrodes, respectively, and

wherein the first bumps are provided in the through-holes so as to be electrically connected to the through-electrodes, respectively.

4. The semiconductor package as claimed in claim 1 , further comprising:

a pad disposed between each of the through-electrodes and each of the first bumps.

5. The semiconductor package as claimed in claim 1 , wherein the first bumps include:

a pair of first bumps spaced apart from each other in the first direction by a first distance, the pair of first bumps being immediately adjacent to each other; and

another pair of first bumps spaced apart from each other in the first direction by a second distance greater than the first distance,

wherein the at least one second bump is provided between the another pair of first bumps.

6. The semiconductor package as claimed in claim 5 , wherein the at least one second bump includes a plurality of second bumps,

wherein the second bumps immediately adjacent to each other are spaced apart from each other in the first direction by a third distance, and

wherein the third distance is substantially equal to or smaller than the first distance.

7. The semiconductor package as claimed in claim 6 , wherein the first bump and the second bump immediately adjacent to each other are spaced apart from each other in the first direction by a fourth distance, and

wherein the fourth distance is substantially equal to or smaller than the first distance.

8. The semiconductor package as claimed in claim 1 , wherein the first bumps and the at least one second bump have thicknesses in a second direction perpendicular to the top surface of the substrate, and

wherein the thicknesses of the first bumps are substantially equal to the thickness of the at least one second bump.

9. The semiconductor package as claimed in claim 1 , wherein a top surface of the underfill is disposed at a substantially same level as or a higher level than a topmost portion of a top surface of the at least one second bump, based on a top surface of the substrate.

10. A semiconductor package, comprising:

a substrate;

through-electrodes penetrating the substrate;

an insulating pattern on the substrate, the insulating pattern having through-holes exposing the through-electrodes, respectively;

first bumps disposed on the substrate, and connected to the through-electrodes via the through-holes, respectively;

at least one second bump disposed on the insulating pattern, and disposed between the first bumps immediately adjacent to each other, an entire bottom of the at least one second bump being in contact with the insulating pattern and not electrically connected to any through-electrodes; and

an underfill covering the substrate, the insulating pattern, the first bumps, and the at least one second bump,

wherein the at least one second bump is electrically insulated from the through-electrodes by the insulating pattern.

11. The semiconductor package as claimed in claim 10 , wherein a level of a bottom surface of the at least one second bump from a top surface of the substrate is higher than levels of bottom surfaces of the first bumps from the top surface of the substrate.

12. The semiconductor package as claimed in claim 10 , wherein the first bumps spaced are apart from each other in a first direction parallel to a top surface of the substrate, and

wherein the first bumps and the at least one second bump constitute one row in the first direction.

13. The semiconductor package as claimed in claim 10 , further comprising:

a pad disposed between each of the through-electrodes and each of the first bumps.

14. The semiconductor package as claimed in claim 13 , wherein a thickness of the insulating pattern is greater than a thickness of the pad.

15. The semiconductor package as claimed in claim 10 , wherein the first bumps include:

a pair of first bumps spaced apart from each other in a first direction by a first distance, the pair of first bumps being immediately adjacent to each other; and

another pair of first bumps spaced apart from each other in the first direction by a second distance greater than the first distance,

wherein the at least one second bump is provided between the another pair of first bumps.

16. The semiconductor package as claimed in claim 15 , wherein the at least one second bump includes a plurality of second bumps,

wherein the second bumps immediately adjacent to each other are spaced apart from each other in the first direction by a third distance, and

wherein the third distance is substantially equal to or smaller than the first distance.

17. The semiconductor package as claimed in claim 16 , wherein the first bump and the second bump immediately adjacent to each other are spaced apart from each other in the first direction by a fourth distance, and

wherein the fourth distance is substantially equal to or smaller than the first distance.

18. The semiconductor package as claimed in claim 10 , wherein the first bumps and the at least one second bump have thicknesses in a second direction perpendicular to a top surface of the substrate, and

wherein the thicknesses of the first bumps are substantially equal to the thickness of the at least one second bump.

19. The semiconductor package as claimed in claim 10 , wherein a top surface of the underfill is disposed at a substantially same level as or a higher level than a topmost portion of a top surface of the at least one second bump, based on a top surface of the substrate.

20. A semiconductor package, comprising:

a substrate;

through-electrodes penetrating the substrate;

first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively;

at least one second bump disposed between the first bumps, the at least one second bump being electrically insulated from the through-electrodes;

an insulating pattern between the substrate and the at least one second bump; and

an underfill covering the substrate, the first bumps, and the at least one second bump,

wherein the first bumps and the at least one second bump constitute one row in the first direction,

wherein the at least one second bump is disposed at a higher level from the substrate than the first bumps, and

wherein the through-electrodes are only connected to the first bumps from among the first and second bumps.