Semiconductor package and fabricating method thereof
A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
1. A semiconductor package comprising:
a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side;
a semiconductor die mounted on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides;
an interposer comprising:
a top interposer side;
a bottom interposer side;
a plurality of lateral interposer sides; and
a bottom interposer circuit pattern on the bottom interposer side;
a top adhesive that covers the top die side and bonds the top die side to the bottom interposer side;
a vertical interconnect structure comprising:
a top vertical interconnect end that is bonded to the bottom interposer circuit pattern; and
a bottom vertical interconnect end that is bonded to the top substrate circuit pattern; and
an encapsulating material, of a different material from the top adhesive, comprising a top encapsulant side facing the bottom interposer side, a bottom encapsulant side facing the top substrate side, and a plurality of lateral encapsulant sides, where:
the encapsulating material directly contacts the lateral die sides and a lateral side of the top adhesive, and laterally surrounds the vertical interconnect structure; and
the lateral interposer sides and the lateral substrate sides are free of the encapsulating material.
2. The semiconductor package of claim 1 , wherein the top adhesive covers an entirety of the top die side, and the top adhesive directly contacts the top die side.
3. The semiconductor package of claim 1 , wherein
a first lateral encapsulant side of the plurality of lateral encapsulant sides is coplanar with a first lateral substrate side of the plurality of lateral substrate sides and with a first lateral interposer side of the plurality of lateral interposer sides.
4. The semiconductor package of claim 1 , comprising an underfill material, different from the encapsulating material, between the bottom die side and the top substrate side, and where:
the encapsulating material laterally surrounds the underfill material; and
an entirety of each of the lateral encapsulant sides is vertical.
5. The semiconductor package of claim 1 , wherein:
the vertical interconnect structure comprises a solder part and a solderless part; and
no portion of the encapsulating material is vertically higher than the interposer.
6. The semiconductor package of claim 1 , wherein a laterally outermost surface of the semiconductor package comprises a laterally outermost surface of the encapsulating material.
7. The semiconductor package of claim 1 , wherein there is no intervening material directly vertically between the top encapsulant side and the bottom interposer side.
8. A semiconductor package comprising:
a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side;
a semiconductor die mounted on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides;
an interposer comprising:
a top interposer side;
a bottom interposer side;
a plurality of lateral interposer sides; and
a bottom interposer circuit pattern on the bottom interposer side;
a vertical interconnect structure comprising:
a first material comprising a conductive metal; and
a second material, different from the first material, that contacts and laterally surrounds the conductive metal of the first material;
a top vertical interconnect end that is bonded to the bottom interposer circuit pattern; and
a bottom vertical interconnect end that is bonded to the top substrate circuit pattern; and
an encapsulating material, different from the second material, comprising a top encapsulant side facing the bottom interposer side, a bottom encapsulant side facing the top substrate side, and a plurality of lateral encapsulant sides, where:
the encapsulating material laterally surrounds the semiconductor die, and the vertical interconnect structure;
the lateral interposer sides and the lateral substrate sides are free of the encapsulating material; and
the top encapsulant side directly contacts the bottom interposer side.
9. The semiconductor package of claim 8 , wherein the first material is soldered to the top substrate circuit pattern.
10. The semiconductor package of claim 8 , wherein the first material comprises copper.
11. The semiconductor package of claim 10 , wherein the second material comprises a dielectric.
12. The semiconductor package of claim 8 , wherein the first material has a maximum vertical thickness, and the encapsulating material has a maximum vertical thickness that is greater than the maximum vertical thickness of the first material.
13. The semiconductor package of claim 12 , wherein the semiconductor die has a maximum vertical thickness that is less the maximum vertical thickness of the first material.
14. The semiconductor package of claim 8 , wherein the first material has a maximum vertical thickness, and the second material has a maximum vertical thickness that is greater than the maximum vertical thickness of the first material.
15. The semiconductor package of claim 8 , wherein top encapsulant side is higher than the top die side, and the bottom encapsulant side is lower than the bottom die side.
16. A method of manufacturing a semiconductor package, the method comprising:
providing a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side;
providing a semiconductor die mounted on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides;
providing an interposer comprising:
a top interposer side;
a bottom interposer side;
a plurality of lateral interposer sides; and
a bottom interposer circuit pattern on the bottom interposer side;
providing a top adhesive that covers the top die side and bonds the top die side to the bottom interposer side;
providing a vertical interconnect structure comprising:
a top vertical interconnect end that is bonded to the bottom interposer circuit pattern; and
a bottom vertical interconnect end that is bonded to the top substrate circuit pattern; and
providing an encapsulating material, of a different material from the top adhesive, comprising a top encapsulant side facing the bottom interposer side, a bottom encapsulant side facing the top substrate side, and a plurality of lateral encapsulant sides, where:
the encapsulating material directly contacts the lateral die sides and a lateral side of the top adhesive, and laterally surrounds the vertical interconnect structure; and
the lateral interposer sides and the lateral substrate sides are free of the encapsulating material.
17. The method of claim 16 , wherein there is no intervening material directly vertically between the top encapsulant side and the bottom interposer side.
18. The method of claim 16 , wherein the vertical interconnect structure comprises:
a first material comprising a conductive metal; and
a second material, different from the first material, that contacts and laterally surrounds the conductive metal of the first material.
19. The method of claim 18 , wherein:
the first material has a maximum vertical thickness, and the encapsulating material has a maximum vertical thickness that is greater than the maximum vertical thickness of the first material; and
the semiconductor die has a maximum vertical thickness that is less the maximum vertical thickness of the first material.