Gate contact and via structures in semiconductor devices

1. A semiconductor device, comprising:

a substrate;

a fin structure disposed on the substrate;

a source/drain (S/D) region disposed on the fin structure;

a gate structure disposed on the fin structure adjacent to the S/D region,

wherein the gate structure comprises a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack,

wherein the gate capping structure comprises a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap;

a first contact structure disposed within the gate capping structure, wherein a top surface of the first contact structure is substantially coplanar with a top surface of the insulating gate cap; and

a first via structure disposed on the first contact structure.

2. The semiconductor device of claim 1 , wherein the first contact structure is separated from the gate stack by a portion of the conductive gate cap.

3. The semiconductor device of claim 1 , wherein a first portion of the first contact structure is disposed within the conductive gate cap and a second portion of the first contact structure is disposed within the insulating gate cap.

4. The semiconductor device of claim 1 , further comprising an etch stop layer disposed on the gate capping structure, wherein a portion of the first via structure is disposed within the etch stop layer.

5. The semiconductor device of claim 1 , further comprising an interlayer dielectric (ILD) layer disposed over the gate capping structure, wherein a portion of the first via structure is disposed within the ILD layer.

6. The semiconductor device of claim 1 , further comprising:

an etch stop layer disposed on the gate capping structure; and

an interlayer dielectric (ILD) layer disposed on the etch stop layer,

wherein a first portion of the first via structure is disposed within the etch stop layer and a second portion of the first via structure is disposed within the ILD layer, and

wherein the second portion is thicker than the first portion.

7. The semiconductor device of claim 1 , wherein the first contact structure and the first via structure comprise materials different from each other.

8. The semiconductor device of claim 1 , wherein a ratio of a thickness of the first contact structure to a thickness of the first via structure ranges from about 1:2 to about 1:6.

9. The semiconductor device of claim 1 , wherein a ratio of a thickness of the conductive gate cap to a thickness of the insulating gate cap ranges from about 1:1 to about 1:2.

10. The semiconductor device of claim 1 , further comprising a second contact structure on the S/D region.

11. The semiconductor device of claim 10 , further comprising a second via structure on the second contact structure, wherein materials of the first and second via structures are same as each other.

12. A semiconductor device, comprising:

a substrate;

a fin structure disposed on the substrate;

first and second source/drain (S/D) regions disposed on the fin structure;

first and second S/D contact structures disposed on the first and second S/D regions, respectively;

a S/D via structure disposed on the first S/D contact structure;

first and second gate structures disposed on the fin structure, wherein each of the first and second gate structures comprises a gate stack and a gate capping structure;

a gate contact structure disposed within the gate capping structure of the first gate structure; and

a merged via-contact structure disposed on the second S/D contact structure and within the gate capping structure of the second gate structure, wherein a first portion of the merged via-contact structure is disposed in a conductive gate cap of the gate capping structure of the second gate structure.

13. The semiconductor device of claim 12 , wherein a second portion of the merged via-contact structure is disposed with the in an insulating gate cap of the gate capping structure of the second gate structure.

14. The semiconductor device of claim 12 , further comprising a gate via structure disposed on the gate contact structure.

15. A semiconductor device, comprising:

a substrate;

a source/drain (S/D) region disposed on the substrate;

a gate stack disposed on the substrate;

a capping structure disposed on the gate stack; and

a contact structure disposed in the capping structure, wherein the contact structure is separated from the gate stack by a portion of the capping structure, and wherein a top surface of the contact structure is substantially coplanar with a top surface of the capping structure.

16. The semiconductor device of claim 15 , wherein the capping structure comprises:

a conductive gate cap disposed on the gate stack; and

an insulating gate cap disposed on the conductive gate cap.

17. The semiconductor device of claim 15 , wherein the capping structure comprises a conductive gate cap and an insulation cap; and

wherein a first portion of the contact structure is disposed in the conductive gate cap and a second portion of the contact structure is disposed in the insulating cap.

18. The semiconductor device of claim 15 , wherein the capping structure comprises a T-shaped cross-sectional profile.

19. The semiconductor device of claim 12 , wherein the gate contact structure and the merged via contact comprise materials different from each other.

20. The semiconductor device of claim 12 , wherein sidewalls of the merged via contact is in contact with the second S/D contact structure.